Home
Sort by
last modified time
|
relevance
|
path
Repository(s)
applications
arkcompiler
base
build
commonlibrary
developtools
device
docs
domains
drivers
foundation
ide
interface
kernel
napi_generator
productdefine
test
third_party
vendor
select all
invert selection
clear
Full Search
Search through all text tokens(words,strings,identifiers,numbers) in index.
Definition
Only finds symbol definitions(where e.g a variable(function,...) is defined).
Symbol
Only finds symbol(e.g. methods classes,function,variables).
File Path
Path of the source file(use "/").If you want just exact path,enclose it in "".Source files end with: .jar/.bz2/.a/.h/.java...
History
History log comments.
Type
Any
Bzip(2)
C
Clojure
C#
C++
ELF
Erlang
Image file
Fortran
Golang
GZIP
Haskell
Jar
Java
Java class
JavaScript
Lisp
Lua
Pascal
Perl
PHP
Plain Text
PL/SQL
Python
Rust
Scala
Shell script
SQL
Tar
Tcl
Troff
UUEncoded
Visual Basic
XML
Zip
Type of analyzer used to filter file types include with selected(e.g. just C sources).
Help
Searched
refs:required_clk_rate
(Results
1 - 2
of
2
) sorted by relevance
/kernel/linux/linux-6.6/drivers/pwm/
H
A
D
pwm-tegra.c
102
unsigned long rate,
required_clk_rate
;
in tegra_pwm_config()
local
142
*
required_clk_rate
is a reference rate for source clock and
in tegra_pwm_config()
144
* source clock rate as
required_clk_rate
, PWM controller will
in tegra_pwm_config()
147
required_clk_rate
= DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
in tegra_pwm_config()
150
if (
required_clk_rate
> clk_round_rate(pc->clk,
required_clk_rate
))
in tegra_pwm_config()
152
*
required_clk_rate
is a lower bound for the input
in tegra_pwm_config()
156
*
required_clk_rate
to get a clock rate that can meet
in tegra_pwm_config()
159
required_clk_rate
*= 2;
in tegra_pwm_config()
161
err = dev_pm_opp_set_rate(pc->dev,
required_clk_rate
);
in tegra_pwm_config()
[all...]
/kernel/linux/linux-5.10/drivers/pwm/
H
A
D
pwm-tegra.c
100
unsigned long rate,
required_clk_rate
;
in tegra_pwm_config()
local
140
*
required_clk_rate
is a reference rate for source clock and
in tegra_pwm_config()
142
* source clock rate as
required_clk_rate
, PWM controller will
in tegra_pwm_config()
145
required_clk_rate
= DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
in tegra_pwm_config()
148
err = clk_set_rate(pc->clk,
required_clk_rate
);
in tegra_pwm_config()
Completed in 2 milliseconds