Lines Matching refs:required_clk_rate
102 unsigned long rate, required_clk_rate;
142 * required_clk_rate is a reference rate for source clock and
144 * source clock rate as required_clk_rate, PWM controller will
147 required_clk_rate = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WIDTH,
150 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate))
152 * required_clk_rate is a lower bound for the input
156 * required_clk_rate to get a clock rate that can meet
159 required_clk_rate *= 2;
161 err = dev_pm_opp_set_rate(pc->dev, required_clk_rate);