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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c74 * @post_div: post divider
83 static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in amdgpu_pll_get_fb_ref_div() argument
88 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
91 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
92 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
112 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
126 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local
154 post_div_min = pll->post_div; in amdgpu_pll_compute()
155 post_div_max = pll->post_div; in amdgpu_pll_compute()
199 for (post_div in amdgpu_pll_compute()
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H A Datombios_crtc.c585 u32 post_div, in amdgpu_atombios_crtc_program_pll()
612 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
622 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
632 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
649 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
679 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
826 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
852 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
855 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
862 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
576 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) amdgpu_atombios_crtc_program_pll() argument
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H A Damdgpu_atombios.h28 u32 post_div; member
68 u32 post_div; member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c75 * @post_div: post divider
85 unsigned int den, unsigned int post_div, in amdgpu_pll_get_fb_ref_div()
92 ref_div_max = min(100 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
94 ref_div_max = min(128 / post_div, ref_div_max); in amdgpu_pll_get_fb_ref_div()
97 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
98 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
120 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
135 unsigned post_div_min, post_div_max, post_div; in amdgpu_pll_compute() local
163 post_div_min = pll->post_div; in amdgpu_pll_compute()
164 post_div_max = pll->post_div; in amdgpu_pll_compute()
84 amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom, unsigned int den, unsigned int post_div, unsigned int fb_div_max, unsigned int ref_div_max, unsigned int *fb_div, unsigned int *ref_div) amdgpu_pll_get_fb_ref_div() argument
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H A Datombios_crtc.c584 u32 post_div, in amdgpu_atombios_crtc_program_pll()
611 args.v1.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
621 args.v2.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
631 args.v3.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
648 args.v5.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
678 args.v6.ucPostDiv = post_div; in amdgpu_atombios_crtc_program_pll()
825 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
851 pll->post_div = amdgpu_crtc->pll_post_div; in amdgpu_atombios_crtc_set_pll()
854 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
861 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
575 amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, u32 crtc_id, int pll_id, u32 encoder_mode, u32 encoder_id, u32 clock, u32 ref_div, u32 fb_div, u32 frac_fb_div, u32 post_div, int bpc, bool ss_enabled, struct amdgpu_atom_ss *ss) amdgpu_atombios_crtc_program_pll() argument
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H A Damdgpu_atombios.h28 u32 post_div; member
68 u32 post_div; member
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
59 if (post_div == 2) in radeon_legacy_get_engine_clock()
61 else if (post_div == 3) in radeon_legacy_get_engine_clock()
63 else if (post_div == 4) in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
89 if (post_div == 2) in radeon_legacy_get_memory_clock()
91 else if (post_div == 3) in radeon_legacy_get_memory_clock()
93 else if (post_div in radeon_legacy_get_memory_clock()
351 calc_eng_mem_clock(struct radeon_device *rdev, uint32_t req_clock, int *fb_div, int *post_div) calc_eng_mem_clock() argument
394 int fb_div, post_div; radeon_legacy_set_engine_clock() local
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H A Dradeon_display.c923 * @post_div: post divider
932 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument
937 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div()
940 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div()
941 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
961 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
975 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local
1006 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1007 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1051 for (post_div in radeon_compute_pll_avivo()
1138 uint32_t post_div; radeon_compute_pll_legacy() local
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H A Drv730_dpm.c64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
142 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
143 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
155 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
156 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
H A Dradeon_legacy_tv.c856 int post_div; in get_post_div() local
858 case 1: post_div = 0; break; in get_post_div()
859 case 2: post_div = 1; break; in get_post_div()
860 case 3: post_div = 4; break; in get_post_div()
861 case 4: post_div = 2; break; in get_post_div()
862 case 6: post_div = 6; break; in get_post_div()
863 case 8: post_div = 3; break; in get_post_div()
864 case 12: post_div = 7; break; in get_post_div()
866 default: post_div = 5; break; in get_post_div()
868 return post_div; in get_post_div()
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H A Drv740_dpm.c143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
217 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
234 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
247 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
H A Dradeon_uvd.c922 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local
925 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div()
926 post_div = pd_min; in radeon_uvd_calc_upll_post_div()
929 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div()
930 post_div += 1; in radeon_uvd_calc_upll_post_div()
933 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div()
934 post_div += 1; in radeon_uvd_calc_upll_post_div()
936 return post_div; in radeon_uvd_calc_upll_post_div()
H A Dradeon_legacy_crtc.c756 } *post_div, post_divs[] = { in radeon_set_pll() local
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
827 if (!post_div->divider) in radeon_set_pll()
828 post_div = &post_divs[0]; in radeon_set_pll()
843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
H A Drs780_dpm.c89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
455 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling()
457 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling()
990 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local
993 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local
1015 (post_div * ref_div); in rs780_dpm_get_current_sclk()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
58 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
59 if (post_div == 2) in radeon_legacy_get_engine_clock()
61 else if (post_div == 3) in radeon_legacy_get_engine_clock()
63 else if (post_div == 4) in radeon_legacy_get_engine_clock()
73 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
88 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
89 if (post_div == 2) in radeon_legacy_get_memory_clock()
91 else if (post_div == 3) in radeon_legacy_get_memory_clock()
93 else if (post_div in radeon_legacy_get_memory_clock()
351 calc_eng_mem_clock(struct radeon_device *rdev, uint32_t req_clock, int *fb_div, int *post_div) calc_eng_mem_clock() argument
394 int fb_div, post_div; radeon_legacy_set_engine_clock() local
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H A Dradeon_display.c921 * @post_div: post divider
930 static void avivo_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div, in avivo_get_fb_ref_div() argument
935 ref_div_max = max(min(100 / post_div, ref_div_max), 1u); in avivo_get_fb_ref_div()
938 *ref_div = min(max(den/post_div, 1u), ref_div_max); in avivo_get_fb_ref_div()
939 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
960 * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
974 unsigned post_div_min, post_div_max, post_div; in radeon_compute_pll_avivo() local
1005 post_div_min = pll->post_div; in radeon_compute_pll_avivo()
1006 post_div_max = pll->post_div; in radeon_compute_pll_avivo()
1050 for (post_div in radeon_compute_pll_avivo()
1135 uint32_t post_div; radeon_compute_pll_legacy() local
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H A Drv730_dpm.c62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_sclk_value()
140 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_mclk_value()
141 (dividers.post_div & 0xf) + 2; in rv730_populate_mclk_value()
153 mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_mclk_value()
154 mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); in rv730_populate_mclk_value()
H A Dradeon_legacy_tv.c857 int post_div; in get_post_div() local
859 case 1: post_div = 0; break; in get_post_div()
860 case 2: post_div = 1; break; in get_post_div()
861 case 3: post_div = 4; break; in get_post_div()
862 case 4: post_div = 2; break; in get_post_div()
863 case 6: post_div = 6; break; in get_post_div()
864 case 8: post_div = 3; break; in get_post_div()
865 case 12: post_div = 7; break; in get_post_div()
867 default: post_div = 5; break; in get_post_div()
869 return post_div; in get_post_div()
[all...]
H A Drv740_dpm.c142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
216 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
233 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
H A Dradeon_uvd.c912 unsigned post_div = vco_freq / target_freq; in radeon_uvd_calc_upll_post_div() local
915 if (post_div < pd_min) in radeon_uvd_calc_upll_post_div()
916 post_div = pd_min; in radeon_uvd_calc_upll_post_div()
919 if ((vco_freq / post_div) > target_freq) in radeon_uvd_calc_upll_post_div()
920 post_div += 1; in radeon_uvd_calc_upll_post_div()
923 if (post_div > pd_even && post_div % 2) in radeon_uvd_calc_upll_post_div()
924 post_div += 1; in radeon_uvd_calc_upll_post_div()
926 return post_div; in radeon_uvd_calc_upll_post_div()
H A Dradeon_legacy_crtc.c756 } *post_div, post_divs[] = { in radeon_set_pll() local
822 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { in radeon_set_pll()
823 if (post_div->divider == post_divider) in radeon_set_pll()
827 if (!post_div->divider) in radeon_set_pll()
828 post_div = &post_divs[0]; in radeon_set_pll()
843 pll_fb_post_div = (feedback_div | (post_div->bitvalue << 16)); in radeon_set_pll()
H A Drs780_dpm.c89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
454 (min_dividers.post_div != max_dividers.post_div) || in rs780_set_engine_clock_scaling()
456 (max_dividers.post_div != current_max_dividers.post_div)) in rs780_set_engine_clock_scaling()
989 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_debugfs_print_current_performance_level() local
992 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1011 u32 post_div = ((func_cntl & SPLL_SW_HILEN_MASK) >> SPLL_SW_HILEN_SHIFT) + 1 + in rs780_dpm_get_current_sclk() local
1014 (post_div * ref_div); in rs780_dpm_get_current_sclk()
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-stm32f4.c1760 const struct stm32f4_pll_post_div_data *post_div; in stm32f4_rcc_init() local
1763 post_div = &post_div_data[n]; in stm32f4_rcc_init()
1765 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init()
1766 post_div->parent, in stm32f4_rcc_init()
1767 post_div->flag, in stm32f4_rcc_init()
1768 base + post_div->offset, in stm32f4_rcc_init()
1769 post_div->shift, in stm32f4_rcc_init()
1770 post_div->width, in stm32f4_rcc_init()
1771 post_div->flag_div, in stm32f4_rcc_init()
1772 post_div in stm32f4_rcc_init()
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/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-stm32f4.c1761 const struct stm32f4_pll_post_div_data *post_div; in stm32f4_rcc_init() local
1764 post_div = &post_div_data[n]; in stm32f4_rcc_init()
1766 hw = clk_register_pll_div(post_div->name, in stm32f4_rcc_init()
1767 post_div->parent, in stm32f4_rcc_init()
1768 post_div->flag, in stm32f4_rcc_init()
1769 base + post_div->offset, in stm32f4_rcc_init()
1770 post_div->shift, in stm32f4_rcc_init()
1771 post_div->width, in stm32f4_rcc_init()
1772 post_div->flag_div, in stm32f4_rcc_init()
1773 post_div in stm32f4_rcc_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c55 u32 post_div = 0; in read_pll() local
61 post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16); in read_pll()
64 post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16; in read_pll()
74 clock = clock / post_div; in read_pll()

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