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Searched refs:phy_modify (Results 1 - 25 of 35) sorted by relevance

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/kernel/linux/linux-5.10/drivers/net/phy/
H A Dvitesse.c130 phy_modify(phydev, 0x0c, 0x0300, 0x0200); in vsc73xx_config_init()
134 phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061); in vsc73xx_config_init()
146 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
149 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc738x_config_init()
150 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc738x_config_init()
153 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
163 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
173 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
188 phy_modify(phydev, 0x16, 0x0fc0, 0x0240); in vsc738x_config_init()
189 phy_modify(phyde in vsc738x_config_init()
[all...]
H A Dnxp-tja11xx.c106 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
155 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, in tja11xx_wakeup()
263 ret = phy_modify(phydev, MII_CFG1, in tja11xx_config_init()
285 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, in tja11xx_config_init()
H A Dmarvell.c713 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL, in m88e3016_config_init()
729 return phy_modify(phydev, MII_M1111_PHY_EXT_SR, in m88e1111_config_init_hwcfg_mode()
750 return phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_config_init_rgmii_delays()
878 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_set_downshift()
942 err = phy_modify(phydev, MII_M1011_PHY_SCR, in m88e1011_set_downshift()
1039 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1046 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, 0, in m88e1510_config_init()
1159 err = phy_modify(phydev, 0x1e, 0x0fc0, in m88e1145_config_init_rgmii()
1285 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
1927 ret = phy_modify(phyde in marvell_cable_test_start_common()
[all...]
H A Dicplus.c243 err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, in ip101a_g_config_init()
250 err = phy_modify(phydev, IP101G_DIGITAL_IO_SPEC_CTRL, in ip101a_g_config_init()
H A Ddp83867.c408 return phy_modify(phydev, DP83867_CFG2, in dp83867_set_downshift()
615 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, in dp83867_config_init()
811 err = phy_modify(phydev, MII_DP83867_PHYCTRL, in dp83867_phy_reset()
H A Ddp83869.c433 return phy_modify(phydev, DP83869_CFG2, in dp83869_set_downshift()
634 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83869_configure_fiber()
751 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, in dp83869_config_init()
H A Ddp83822.c392 err = phy_modify(phydev, MII_DP83822_CTRL_2, in dp83822_config_init()
420 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83822_config_init()
H A Dphy-core.c620 * phy_modify - Convenience function for modifying a given PHY register
630 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) in phy_modify() function
640 EXPORT_SYMBOL_GPL(phy_modify); variable
H A Dadin.c326 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, in adin_set_downshift()
379 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2, in adin_set_edpd()
H A Dbcm54140.c479 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); in bcm54140_b0_workaround()
483 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); in bcm54140_b0_workaround()
H A Dphy_device.c1952 return phy_modify(phydev, MII_BMCR, in genphy_setup_forced()
2048 return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, in genphy_restart_aneg()
2134 err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100, in genphy_c37_config_aneg()
2433 ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res); in genphy_soft_reset()
2536 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, in genphy_loopback()
/kernel/linux/linux-6.6/drivers/net/phy/
H A Dvitesse.c135 phy_modify(phydev, 0x0c, 0x0300, 0x0200); in vsc73xx_config_init()
139 phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061); in vsc73xx_config_init()
151 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
154 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc738x_config_init()
155 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc738x_config_init()
158 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
168 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
178 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
193 phy_modify(phydev, 0x16, 0x0fc0, 0x0240); in vsc738x_config_init()
194 phy_modify(phyde in vsc738x_config_init()
[all...]
H A Dnxp-tja11xx.c121 ret = phy_modify(phydev, reg, mask, set); in phy_modify_check()
170 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK, in tja11xx_wakeup()
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val); in tja11xx_config_init()
343 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO, in tja11xx_config_init()
H A Ddp83867.c451 return phy_modify(phydev, DP83867_CFG2, in dp83867_set_downshift()
749 ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN, in dp83867_config_init()
945 err = phy_modify(phydev, MII_DP83867_PHYCTRL, in dp83867_phy_reset()
996 return phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, in dp83867_loopback()
1015 return phy_modify(phydev, DP83867_LEDCR2, in dp83867_led_brightness_set()
H A Dmarvell.c803 ret = phy_modify(phydev, MII_88E3016_PHY_SPEC_CTRL, in m88e3016_config_init()
819 return phy_modify(phydev, MII_M1111_PHY_EXT_SR, in m88e1111_config_init_hwcfg_mode()
845 return phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_config_init_rgmii_delays()
925 err = phy_modify(phydev, MII_M1111_PHY_EXT_SR, in m88e1111_config_init_1000basex()
1015 err = phy_modify(phydev, MII_M1111_PHY_EXT_CR, in m88e1111_set_downshift()
1079 err = phy_modify(phydev, MII_M1011_PHY_SCR, in m88e1011_set_downshift()
1245 err = phy_modify(phydev, MII_88E1510_GEN_CTRL_REG_1, in m88e1510_config_init()
1362 err = phy_modify(phydev, 0x1e, 0x0fc0, in m88e1145_config_init_rgmii()
1491 ret = phy_modify(phydev, MII_88E1540_COPPER_CTRL3, in m88e1540_set_fld()
2022 err = phy_modify(phyde in m88e1510_loopback()
[all...]
H A Ddp83869.c468 return phy_modify(phydev, DP83869_CFG2, in dp83869_set_downshift()
669 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83869_configure_fiber()
797 ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN, in dp83869_config_init()
H A Ddp83822.c423 err = phy_modify(phydev, MII_DP83822_CTRL_2, in dp83822_config_init()
451 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83822_config_init()
H A Dat803x.c478 ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL); in at803x_set_wol()
491 ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0); in at803x_set_wol()
592 phy_modify(phydev, MII_BMCR, 0, value); in at803x_suspend()
599 return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0); in at803x_resume()
1067 return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0); in at803x_config_init()
1692 phy_modify(phydev, MII_BMCR, mask, 0); in qca83xx_suspend()
H A Dbcm54140.c479 ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); in bcm54140_b0_workaround()
483 ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); in bcm54140_b0_workaround()
H A Dadin.c361 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3, in adin_set_downshift()
414 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2, in adin_set_edpd()
H A Dphy-core.c704 * phy_modify - Convenience function for modifying a given PHY register
714 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set) in phy_modify() function
724 EXPORT_SYMBOL_GPL(phy_modify); variable
H A Dphy_device.c2099 return phy_modify(phydev, MII_BMCR, in genphy_setup_forced()
2190 return phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, in genphy_restart_aneg()
2279 err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100, in genphy_c37_config_aneg()
2582 ret = phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, res); in genphy_soft_reset()
2709 phy_modify(phydev, MII_BMCR, ~0, ctl); in genphy_loopback()
2717 phy_modify(phydev, MII_BMCR, BMCR_LOOPBACK, 0); in genphy_loopback()
/kernel/linux/linux-6.6/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c482 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); in rtl8168d_1_hw_phy_config()
483 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); in rtl8168d_1_hw_phy_config()
499 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_1_hw_phy_config()
520 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_2_hw_phy_config()
1081 phy_modify(phydev, 0x17, 0xff00, 0x0800); in rtl8125b_hw_phy_config()
/kernel/linux/linux-5.10/drivers/net/ethernet/realtek/
H A Dr8169_phy_config.c468 phy_modify(phydev, 0x0b, 0x00ef, 0x0010); in rtl8168d_1_hw_phy_config()
469 phy_modify(phydev, 0x0c, 0x5d00, 0xa200); in rtl8168d_1_hw_phy_config()
503 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_1_hw_phy_config()
541 phy_modify(phydev, 0x02, 0x0600, 0x0100); in rtl8168d_2_hw_phy_config()
1284 phy_modify(phydev, 0x17, 0xff00, 0x0800); in rtl8125b_hw_phy_config()
/kernel/linux/linux-5.10/include/linux/
H A Dphy.h1079 int phy_modify(struct phy_device *phydev, u32 regnum, u16 mask, u16 set);
1125 return phy_modify(phydev, regnum, 0, val); in phy_set_bits()
1136 return phy_modify(phydev, regnum, val, 0); in phy_clear_bits()

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