| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 94 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
105 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
187 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value()
205 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
247 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
270 memory_clock); in rv740_populate_mclk_value()
275 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
409 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
413 if ((memory_clock < 10000) || (memory_clock > 4750 in rv740_get_mclk_frequency_ratio()
186 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv740_populate_mclk_value() argument
[all...] |
| H A D | cypress_dpm.c | 475 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value()
502 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
556 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value()
579 memory_clock); in cypress_populate_mclk_value()
602 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
616 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio()
622 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
624 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
627 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
629 if (memory_clock < 6500 in cypress_get_mclk_frequency_ratio()
474 cypress_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) cypress_populate_mclk_value() argument
615 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, u32 memory_clock, bool strobe_mode) cypress_get_mclk_frequency_ratio() argument
908 cypress_calculate_burst_time(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock) cypress_calculate_burst_time() argument
[all...] |
| H A D | rv770_dpm.h | 184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
|
| H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
|
| H A D | rv730_dpm.c | 119 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value()
135 memory_clock, false, ÷rs); in rv730_populate_mclk_value()
167 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
187 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
118 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) rv730_populate_mclk_value() argument
|
| H A D | ci_dpm.c | 155 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
156 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
2482 const u32 memory_clock, in ci_register_patching_mc_arb()
2494 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2498 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2774 u32 memory_clock, in ci_calculate_mclk_params()
2792 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2819 freq_nom = memory_clock * in ci_calculate_mclk_params()
2480 ci_register_patching_mc_arb(struct radeon_device *rdev, const u32 engine_clock, const u32 memory_clock, u32 *dram_timimg2) ci_register_patching_mc_arb() argument
2773 ci_calculate_mclk_params(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dll_state_on) ci_calculate_mclk_params() argument
2860 ci_populate_single_memory_level(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *memory_level) ci_populate_single_memory_level() argument
4703 ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, const u32 memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data) ci_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 93 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) in rv740_get_dll_speed() argument
104 data_rate = (u16)(memory_clock * factor / 1000); in rv740_get_dll_speed()
186 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value()
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
246 u32 vco_freq = memory_clock * dividers.post_div; in rv740_populate_mclk_value()
269 memory_clock); in rv740_populate_mclk_value()
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
408 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) in rv740_get_mclk_frequency_ratio() argument
412 if ((memory_clock < 10000) || (memory_clock > 4750 in rv740_get_mclk_frequency_ratio()
185 rv740_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk) rv740_populate_mclk_value() argument
[all...] |
| H A D | cypress_dpm.c | 473 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value()
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
554 u32 vco_freq = memory_clock * dividers.post_div; in cypress_populate_mclk_value()
577 memory_clock); in cypress_populate_mclk_value()
600 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in cypress_populate_mclk_value()
614 u32 memory_clock, bool strobe_mode) in cypress_get_mclk_frequency_ratio()
620 if (memory_clock < 10000) in cypress_get_mclk_frequency_ratio()
622 else if (memory_clock > 47500) in cypress_get_mclk_frequency_ratio()
625 mc_para_index = (u8)((memory_clock - 10000) / 2500); in cypress_get_mclk_frequency_ratio()
627 if (memory_clock < 6500 in cypress_get_mclk_frequency_ratio()
472 cypress_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, RV7XX_SMC_MCLK_VALUE *mclk, bool strobe_mode, bool dll_state_on) cypress_populate_mclk_value() argument
613 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev, u32 memory_clock, bool strobe_mode) cypress_get_mclk_frequency_ratio() argument
906 cypress_calculate_burst_time(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock) cypress_calculate_burst_time() argument
[all...] |
| H A D | rv770_dpm.h | 184 u32 engine_clock, u32 memory_clock,
205 u32 engine_clock, u32 memory_clock,
212 u8 rv740_get_mclk_frequency_ratio(u32 memory_clock);
213 u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock);
|
| H A D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
157 u32 memory_clock, bool strobe_mode);
|
| H A D | si_dpm.h | 237 u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
238 u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
|
| H A D | rv730_dpm.c | 117 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value()
133 memory_clock, false, ÷rs); in rv730_populate_mclk_value()
165 u32 vco_freq = memory_clock * post_divider; in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
116 rv730_populate_mclk_value(struct radeon_device *rdev, u32 engine_clock, u32 memory_clock, LPRV7XX_SMC_MCLK_VALUE mclk) rv730_populate_mclk_value() argument
|
| H A D | ci_dpm.c | 2458 const u32 memory_clock, in ci_register_patching_mc_arb()
2470 if ((memory_clock > 100000) && (memory_clock <= 125000)) { in ci_register_patching_mc_arb()
2474 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) { in ci_register_patching_mc_arb()
2750 u32 memory_clock, in ci_calculate_mclk_params()
2768 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); in ci_calculate_mclk_params()
2795 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2797 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div); in ci_calculate_mclk_params()
2822 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
2456 ci_register_patching_mc_arb(struct radeon_device *rdev, const u32 engine_clock, const u32 memory_clock, u32 *dram_timimg2) ci_register_patching_mc_arb() argument
2749 ci_calculate_mclk_params(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dll_state_on) ci_calculate_mclk_params() argument
2836 ci_populate_single_memory_level(struct radeon_device *rdev, u32 memory_clock, SMU7_Discrete_MemoryLevel *memory_level) ci_populate_single_memory_level() argument
4679 ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, const u32 memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data) ci_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1046 uint32_t memory_clock, in iceland_calculate_mclk_params()
1068 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params()
1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 6500 in iceland_get_mclk_frequency_ratio()
1044 iceland_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) iceland_calculate_mclk_params() argument
1195 iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) iceland_get_ddr3_mclk_frequency_ratio() argument
1210 iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) iceland_populate_phase_value_based_on_mclk() argument
1227 iceland_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *memory_level ) iceland_populate_single_memory_level() argument
1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) iceland_populate_memory_timing_parameters() argument
1728 iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU71_Discrete_MCRegisterSet *mc_reg_table_data ) iceland_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| H A D | ci_smumgr.c | 1024 uint32_t memory_clock, in ci_calculate_mclk_params()
1045 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params()
1077 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1079 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1104 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1118 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument
1124 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1126 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1129 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio()
1131 if (memory_clock < 6500 in ci_get_mclk_frequency_ratio()
1022 ci_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) ci_calculate_mclk_params() argument
1142 ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) ci_get_ddr3_mclk_frequency_ratio() argument
1156 ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) ci_populate_phase_value_based_on_mclk() argument
1173 ci_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *memory_level ) ci_populate_single_memory_level() argument
1620 ci_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs ) ci_populate_memory_timing_parameters() argument
1761 ci_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data ) ci_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| H A D | tonga_smumgr.c | 789 uint32_t memory_clock, in tonga_calculate_mclk_params()
811 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params()
871 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
873 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
906 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
920 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
931 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 6500 in tonga_get_mclk_frequency_ratio()
787 tonga_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) tonga_calculate_mclk_params() argument
944 tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) tonga_get_ddr3_mclk_frequency_ratio() argument
959 tonga_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *memory_level ) tonga_populate_single_memory_level() argument
1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) tonga_populate_memory_timing_parameters() argument
2106 tonga_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU72_Discrete_MCRegisterSet *mc_reg_table_data ) tonga_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | iceland_smumgr.c | 1046 uint32_t memory_clock, in iceland_calculate_mclk_params()
1068 memory_clock, &mpll_param, strobe_mode); in iceland_calculate_mclk_params()
1119 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1121 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in iceland_calculate_mclk_params()
1155 mclk->MclkFrequency = memory_clock; in iceland_calculate_mclk_params()
1169 static uint8_t iceland_get_mclk_frequency_ratio(uint32_t memory_clock, in iceland_get_mclk_frequency_ratio() argument
1175 if (memory_clock < 12500) { in iceland_get_mclk_frequency_ratio()
1177 } else if (memory_clock > 47500) { in iceland_get_mclk_frequency_ratio()
1180 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in iceland_get_mclk_frequency_ratio()
1183 if (memory_clock < 6500 in iceland_get_mclk_frequency_ratio()
1044 iceland_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) iceland_calculate_mclk_params() argument
1195 iceland_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) iceland_get_ddr3_mclk_frequency_ratio() argument
1210 iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) iceland_populate_phase_value_based_on_mclk() argument
1227 iceland_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU71_Discrete_MemoryLevel *memory_level ) iceland_populate_single_memory_level() argument
1582 iceland_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU71_Discrete_MCArbDramTimingTableEntry *arb_regs ) iceland_populate_memory_timing_parameters() argument
1728 iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU71_Discrete_MCRegisterSet *mc_reg_table_data ) iceland_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| H A D | ci_smumgr.c | 1025 uint32_t memory_clock, in ci_calculate_mclk_params()
1046 memory_clock, &mpll_param, strobe_mode); in ci_calculate_mclk_params()
1078 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1080 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in ci_calculate_mclk_params()
1105 mclk->MclkFrequency = memory_clock; in ci_calculate_mclk_params()
1119 static uint8_t ci_get_mclk_frequency_ratio(uint32_t memory_clock, in ci_get_mclk_frequency_ratio() argument
1125 if (memory_clock < 12500) in ci_get_mclk_frequency_ratio()
1127 else if (memory_clock > 47500) in ci_get_mclk_frequency_ratio()
1130 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in ci_get_mclk_frequency_ratio()
1132 if (memory_clock < 6500 in ci_get_mclk_frequency_ratio()
1023 ci_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) ci_calculate_mclk_params() argument
1143 ci_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) ci_get_ddr3_mclk_frequency_ratio() argument
1157 ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl, uint32_t memory_clock, uint32_t *p_shed) ci_populate_phase_value_based_on_mclk() argument
1174 ci_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU7_Discrete_MemoryLevel *memory_level ) ci_populate_single_memory_level() argument
1621 ci_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs ) ci_populate_memory_timing_parameters() argument
1762 ci_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU7_Discrete_MCRegisterSet *mc_reg_table_data ) ci_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| H A D | tonga_smumgr.c | 789 uint32_t memory_clock, in tonga_calculate_mclk_params()
811 memory_clock, &mpll_param, strobe_mode); in tonga_calculate_mclk_params()
871 freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
873 freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider); in tonga_calculate_mclk_params()
906 mclk->MclkFrequency = memory_clock; in tonga_calculate_mclk_params()
920 static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock, in tonga_get_mclk_frequency_ratio() argument
926 if (memory_clock < 12500) in tonga_get_mclk_frequency_ratio()
928 else if (memory_clock > 47500) in tonga_get_mclk_frequency_ratio()
931 mc_para_index = (uint8_t)((memory_clock - 10000) / 2500); in tonga_get_mclk_frequency_ratio()
933 if (memory_clock < 6500 in tonga_get_mclk_frequency_ratio()
787 tonga_calculate_mclk_params( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *mclk, bool strobe_mode, bool dllStateOn ) tonga_calculate_mclk_params() argument
944 tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock) tonga_get_ddr3_mclk_frequency_ratio() argument
959 tonga_populate_single_memory_level( struct pp_hwmgr *hwmgr, uint32_t memory_clock, SMU72_Discrete_MemoryLevel *memory_level ) tonga_populate_single_memory_level() argument
1457 tonga_populate_memory_timing_parameters( struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock, struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs ) tonga_populate_memory_timing_parameters() argument
2106 tonga_convert_mc_reg_table_entry_to_smc( struct pp_hwmgr *hwmgr, const uint32_t memory_clock, SMU72_Discrete_MCRegisterSet *mc_reg_table_data ) tonga_convert_mc_reg_table_entry_to_smc() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.h | 285 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
288 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
307 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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| H A D | smu7_hwmgr.c | 3015 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3016 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3063 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3067 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
3078 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3087 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules()
3088 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
3090 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3091 smu7_ps->performance_levels[1].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3093 if (smu7_ps->performance_levels[1].memory_clock < in smu7_apply_state_adjust_rules()
3424 uint32_t engine_clock, memory_clock; smu7_get_pp_table_entry_callback_func_v0() local
[all...] |
| H A D | hardwaremanager.c | 397 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
407 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.h | 299 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
303 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
322 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
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| H A D | smu7_hwmgr.c | 3348 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) in smu7_apply_state_adjust_rules()
3349 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; in smu7_apply_state_adjust_rules()
3402 mclk = smu7_ps->performance_levels[0].memory_clock; in smu7_apply_state_adjust_rules()
3408 [smu7_ps->performance_level_count - 1].memory_clock; in smu7_apply_state_adjust_rules()
3419 smu7_ps->performance_levels[0].memory_clock = mclk; in smu7_apply_state_adjust_rules()
3428 if (mclk < smu7_ps->performance_levels[1].memory_clock) in smu7_apply_state_adjust_rules()
3429 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
3442 smu7_ps->performance_levels[0].memory_clock) && in smu7_apply_state_adjust_rules()
3444 smu7_ps->performance_levels[1].memory_clock)) { in smu7_apply_state_adjust_rules()
3458 mclk = smu7_ps->performance_levels[1].memory_clock; in smu7_apply_state_adjust_rules()
3798 uint32_t engine_clock, memory_clock; smu7_get_pp_table_entry_callback_func_v0() local
[all...] |
| H A D | hardwaremanager.c | 401 pclock_info->min_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
411 pclock_info->max_mem_clk = performance_level.memory_clock; in phm_get_clock_info()
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