| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 124 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
137 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
141 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
160 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
199 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
205 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
209 ibias = rv770_map_clkf_to_ibias(rdev, dividers in rv740_populate_mclk_value()
[all...] |
| H A D | rv730_dpm.c | 44 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
57 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
61 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
63 if (dividers.enable_post_div) in rv730_populate_sclk_value()
64 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
65 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
74 if (dividers.enable_post_div) in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
81 spll_func_cntl |= SPLL_LOLEN(dividers in rv730_populate_sclk_value()
130 struct atom_clock_dividers dividers; rv730_populate_mclk_value() local
[all...] |
| H A D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency()
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) in rv6xx_program_engine_spread_spectrum()
525 rv6xx_calculate_vco_frequency(u32 ref_clock, struct atom_clock_dividers *dividers, u32 fb_divider_scale) rv6xx_calculate_vco_frequency() argument
600 struct atom_clock_dividers dividers; rv6xx_program_mclk_stepping_entry() local
630 rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, u32 requested_memory_clock, u32 ref_clk, struct atom_clock_dividers *dividers, u32 *vco_freq) rv6xx_find_memory_clock_with_highest_vco() argument
656 struct atom_clock_dividers dividers; rv6xx_program_mclk_spread_spectrum_parameters() local
1935 struct atom_clock_dividers dividers; rv6xx_dpm_init() local
[all...] |
| H A D | rv770_dpm.c | 320 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider()
332 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
333 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
402 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
410 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
414 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
419 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
421 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
432 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers in rv770_populate_mclk_value()
317 rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, u32 reference_clock, bool gddr5, struct atom_clock_dividers *dividers, u32 *clkf, u32 *clkfrac) rv770_calculate_fractional_mpll_feedback_divider() argument
488 struct atom_clock_dividers dividers; rv770_populate_sclk_value() local
2346 struct atom_clock_dividers dividers; rv770_dpm_init() local
[all...] |
| H A D | cypress_dpm.c | 495 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
502 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
510 dividers.post_div = 1; in cypress_populate_mclk_value()
513 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
522 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
523 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
526 if (dividers.vco_mode) in cypress_populate_mclk_value()
537 mpll_dq_func_cntl |= CLKR(dividers in cypress_populate_mclk_value()
2030 struct atom_clock_dividers dividers; cypress_dpm_init() local
[all...] |
| H A D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1034 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1045 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1049 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1052 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| H A D | rv740_dpm.c | 123 struct atom_clock_dividers dividers; in rv740_populate_sclk_value() local
136 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
140 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
142 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
147 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
148 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); in rv740_populate_sclk_value()
159 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
198 struct atom_clock_dividers dividers; in rv740_populate_mclk_value() local
204 memory_clock, false, ÷rs); in rv740_populate_mclk_value()
208 ibias = rv770_map_clkf_to_ibias(rdev, dividers in rv740_populate_mclk_value()
[all...] |
| H A D | rv730_dpm.c | 42 struct atom_clock_dividers dividers; in rv730_populate_sclk_value() local
55 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
59 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
61 if (dividers.enable_post_div) in rv730_populate_sclk_value()
62 post_divider = ((dividers.post_div >> 4) & 0xf) + in rv730_populate_sclk_value()
63 (dividers.post_div & 0xf) + 2; in rv730_populate_sclk_value()
72 if (dividers.enable_post_div) in rv730_populate_sclk_value()
77 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
78 spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); in rv730_populate_sclk_value()
79 spll_func_cntl |= SPLL_LOLEN(dividers in rv730_populate_sclk_value()
128 struct atom_clock_dividers dividers; rv730_populate_mclk_value() local
[all...] |
| H A D | rv6xx_dpm.c | 142 struct atom_clock_dividers dividers; in rv6xx_convert_clock_to_stepping() local
145 clock, false, ÷rs); in rv6xx_convert_clock_to_stepping()
149 if (dividers.enable_post_div) in rv6xx_convert_clock_to_stepping()
150 step->post_divider = 2 + (dividers.post_div & 0xF) + (dividers.post_div >> 4); in rv6xx_convert_clock_to_stepping()
526 struct atom_clock_dividers *dividers, in rv6xx_calculate_vco_frequency()
529 return ref_clock * ((dividers->fb_div & ~1) << fb_divider_scale) / in rv6xx_calculate_vco_frequency()
530 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
553 struct atom_clock_dividers dividers; in rv6xx_program_engine_spread_spectrum() local
560 if (radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, clock, false, ÷rs) in rv6xx_program_engine_spread_spectrum()
525 rv6xx_calculate_vco_frequency(u32 ref_clock, struct atom_clock_dividers *dividers, u32 fb_divider_scale) rv6xx_calculate_vco_frequency() argument
600 struct atom_clock_dividers dividers; rv6xx_program_mclk_stepping_entry() local
630 rv6xx_find_memory_clock_with_highest_vco(struct radeon_device *rdev, u32 requested_memory_clock, u32 ref_clk, struct atom_clock_dividers *dividers, u32 *vco_freq) rv6xx_find_memory_clock_with_highest_vco() argument
656 struct atom_clock_dividers dividers; rv6xx_program_mclk_spread_spectrum_parameters() local
1935 struct atom_clock_dividers dividers; rv6xx_dpm_init() local
[all...] |
| H A D | rv770_dpm.c | 322 struct atom_clock_dividers *dividers, in rv770_calculate_fractional_mpll_feedback_divider()
334 post_divider = dividers->post_div; in rv770_calculate_fractional_mpll_feedback_divider()
335 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
404 struct atom_clock_dividers dividers; in rv770_populate_mclk_value() local
412 memory_clock, false, ÷rs); in rv770_populate_mclk_value()
416 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
421 ÷rs, &clkf, &clkfrac); in rv770_populate_mclk_value()
423 ret = rv770_encode_yclk_post_div(dividers.post_div, &postdiv_yclk); in rv770_populate_mclk_value()
434 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers in rv770_populate_mclk_value()
319 rv770_calculate_fractional_mpll_feedback_divider(u32 memory_clock, u32 reference_clock, bool gddr5, struct atom_clock_dividers *dividers, u32 *clkf, u32 *clkfrac) rv770_calculate_fractional_mpll_feedback_divider() argument
490 struct atom_clock_dividers dividers; rv770_populate_sclk_value() local
2348 struct atom_clock_dividers dividers; rv770_dpm_init() local
[all...] |
| H A D | cypress_dpm.c | 493 struct atom_clock_dividers dividers; in cypress_populate_mclk_value() local
500 memory_clock, strobe_mode, ÷rs); in cypress_populate_mclk_value()
508 dividers.post_div = 1; in cypress_populate_mclk_value()
511 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div); in cypress_populate_mclk_value()
518 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
519 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); in cypress_populate_mclk_value()
520 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); in cypress_populate_mclk_value()
521 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); in cypress_populate_mclk_value()
524 if (dividers.vco_mode) in cypress_populate_mclk_value()
535 mpll_dq_func_cntl |= CLKR(dividers in cypress_populate_mclk_value()
2028 struct atom_clock_dividers dividers; cypress_dpm_init() local
[all...] |
| H A D | rs780_dpm.c | 78 struct atom_clock_dividers dividers; in rs780_initialize_dpm_power_state() local
83 default_state->sclk_low, false, ÷rs); in rs780_initialize_dpm_power_state()
87 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
88 r600_engine_clock_entry_set_feedback_divider(rdev, 0, dividers.fb_div); in rs780_initialize_dpm_power_state()
89 r600_engine_clock_entry_set_post_divider(rdev, 0, dividers.post_div); in rs780_initialize_dpm_power_state()
91 if (dividers.enable_post_div) in rs780_initialize_dpm_power_state()
1033 struct atom_clock_dividers dividers; in rs780_dpm_force_performance_level() local
1044 ps->sclk_high, false, ÷rs); in rs780_dpm_force_performance_level()
1048 rs780_force_fbdiv(rdev, dividers.fb_div); in rs780_dpm_force_performance_level()
1051 ps->sclk_low, false, ÷rs); in rs780_dpm_force_performance_level()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/modules/color/ |
| H A D | color_gamma.c | 276 struct dividers { struct
1113 struct dividers dividers) in scale_gamma()
1149 dividers.divider1); in scale_gamma()
1151 dividers.divider1); in scale_gamma()
1153 dividers.divider1); in scale_gamma()
1158 dividers.divider2); in scale_gamma()
1160 dividers.divider2); in scale_gamma()
1162 dividers.divider2); in scale_gamma()
1167 dividers in scale_gamma()
1111 scale_gamma(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) scale_gamma() argument
1174 scale_gamma_dx(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) scale_gamma_dx() argument
1242 scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb, const struct regamma_ramp *ramp, struct dividers dividers) scale_user_regamma_ramp() argument
1384 build_evenly_distributed_points( struct gamma_pixel *points, uint32_t numberof_points, struct dividers dividers) build_evenly_distributed_points() argument
1735 struct dividers dividers; calculate_user_regamma_ramp() local
1796 struct dividers dividers; mod_color_calculate_degamma_params() local
2034 struct dividers dividers; mod_color_calculate_regamma_params() local
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/modules/color/ |
| H A D | color_gamma.c | 286 struct dividers { struct
1175 struct dividers dividers) in scale_gamma()
1211 dividers.divider1); in scale_gamma()
1213 dividers.divider1); in scale_gamma()
1215 dividers.divider1); in scale_gamma()
1220 dividers.divider2); in scale_gamma()
1222 dividers.divider2); in scale_gamma()
1224 dividers.divider2); in scale_gamma()
1229 dividers in scale_gamma()
1173 scale_gamma(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) scale_gamma() argument
1236 scale_gamma_dx(struct pwl_float_data *pwl_rgb, const struct dc_gamma *ramp, struct dividers dividers) scale_gamma_dx() argument
1304 scale_user_regamma_ramp(struct pwl_float_data *pwl_rgb, const struct regamma_ramp *ramp, struct dividers dividers) scale_user_regamma_ramp() argument
1459 build_evenly_distributed_points( struct gamma_pixel *points, uint32_t numberof_points, struct dividers dividers) build_evenly_distributed_points() argument
1816 struct dividers dividers; calculate_user_regamma_ramp() local
1880 struct dividers dividers; mod_color_calculate_degamma_params() local
2121 struct dividers dividers; mod_color_calculate_regamma_params() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.c | 244 * @param dividers output parameter: memory PLL dividers
296 * @param dividers output parameter: memory PLL dividers
350 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong()
363 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
364 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
373 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi()
387 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
389 dividers in atomctrl_get_engine_pll_dividers_vi()
348 atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_kong *dividers) atomctrl_get_engine_pll_dividers_kong() argument
370 atomctrl_get_engine_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) atomctrl_get_engine_pll_dividers_vi() argument
408 atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers) atomctrl_get_engine_pll_dividers_ai() argument
439 atomctrl_get_dfs_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) atomctrl_get_dfs_pll_dividers_vi() argument
[all...] |
| H A D | ppatomctrl.h | 291 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
292 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
301 pp_atomctrl_clock_dividers_kong *dividers);
306 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | ppatomctrl.c | 389 pp_atomctrl_clock_dividers_kong *dividers) in atomctrl_get_engine_pll_dividers_kong()
402 dividers->pll_post_divider = pll_parameters.ucPostDiv; in atomctrl_get_engine_pll_dividers_kong()
403 dividers->real_clock = le32_to_cpu(pll_parameters.ulClock); in atomctrl_get_engine_pll_dividers_kong()
412 pp_atomctrl_clock_dividers_vi *dividers) in atomctrl_get_engine_pll_dividers_vi()
426 dividers->pll_post_divider = in atomctrl_get_engine_pll_dividers_vi()
428 dividers->real_clock = in atomctrl_get_engine_pll_dividers_vi()
431 dividers->ul_fb_div.ul_fb_div_frac = in atomctrl_get_engine_pll_dividers_vi()
433 dividers->ul_fb_div.ul_fb_div = in atomctrl_get_engine_pll_dividers_vi()
436 dividers->uc_pll_ref_div = in atomctrl_get_engine_pll_dividers_vi()
438 dividers in atomctrl_get_engine_pll_dividers_vi()
387 atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_kong *dividers) atomctrl_get_engine_pll_dividers_kong() argument
409 atomctrl_get_engine_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) atomctrl_get_engine_pll_dividers_vi() argument
447 atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers) atomctrl_get_engine_pll_dividers_ai() argument
478 atomctrl_get_dfs_pll_dividers_vi( struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers) atomctrl_get_dfs_pll_dividers_vi() argument
[all...] |
| H A D | ppatomctrl.h | 306 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
307 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
316 pp_atomctrl_clock_dividers_kong *dividers);
321 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios.c | 1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers()
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1024 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1026 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1028 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1029 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1030 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1031 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1043 dividers in amdgpu_atombios_get_clock_dividers()
996 amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) amdgpu_atombios_get_clock_dividers() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios.c | 1000 struct atom_clock_dividers *dividers) in amdgpu_atombios_get_clock_dividers()
1007 memset(dividers, 0, sizeof(struct atom_clock_dividers)); in amdgpu_atombios_get_clock_dividers()
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
1024 dividers->enable_post_div = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1026 dividers->enable_dithen = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1028 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in amdgpu_atombios_get_clock_dividers()
1029 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); in amdgpu_atombios_get_clock_dividers()
1030 dividers->ref_div = args.v3.ucRefDiv; in amdgpu_atombios_get_clock_dividers()
1031 dividers->vco_mode = (args.v3.ucCntlFlag & in amdgpu_atombios_get_clock_dividers()
1043 dividers in amdgpu_atombios_get_clock_dividers()
996 amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, u8 clock_type, u32 clock, bool strobe_mode, struct atom_clock_dividers *dividers) amdgpu_atombios_get_clock_dividers() argument
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | polaris10_smumgr.c | 895 struct pp_atomctrl_clock_dividers_ai dividers; in polaris10_calculate_sclk_params() local
903 /* get the engine clock dividers for this clock value */ in polaris10_calculate_sclk_params()
904 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in polaris10_calculate_sclk_params()
906 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in polaris10_calculate_sclk_params()
907 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in polaris10_calculate_sclk_params()
908 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in polaris10_calculate_sclk_params()
909 sclk_setting->PllRange = dividers.ucSclkPllRange; in polaris10_calculate_sclk_params()
911 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in polaris10_calculate_sclk_params()
913 sclk_setting->SSc_En = dividers.ucSscEnable; in polaris10_calculate_sclk_params()
914 sclk_setting->Fcw1_int = dividers in polaris10_calculate_sclk_params()
1058 pp_atomctrl_clock_dividers_vi dividers; polaris10_populate_all_graphic_levels() local
1370 struct pp_atomctrl_clock_dividers_vi dividers; polaris10_populate_smc_vce_level() local
1420 struct pp_atomctrl_clock_dividers_vi dividers; polaris10_populate_smc_samu_level() local
1525 struct pp_atomctrl_clock_dividers_vi dividers; polaris10_populate_smc_uvd_level() local
1924 pp_atomctrl_clock_dividers_vi dividers; polaris10_init_smc_table() local
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| H A D | vegam_smumgr.c | 724 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
732 /* get the engine clock dividers for this clock value */ in vegam_calculate_sclk_params()
733 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
735 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
737 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
738 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
740 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
742 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
743 sclk_setting->Fcw1_int = dividers in vegam_calculate_sclk_params()
1199 struct pp_atomctrl_clock_dividers_vi dividers; vegam_populate_smc_vce_level() local
1312 struct pp_atomctrl_clock_dividers_vi dividers; vegam_populate_smc_uvd_level() local
1930 pp_atomctrl_clock_dividers_vi dividers; vegam_init_smc_table() local
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| H A D | fiji_smumgr.c | 859 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
870 /* get the engine clock dividers for this clock value */ in fiji_calculate_sclk_params()
871 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
874 "Error retrieving Engine Clock dividers from VBIOS.", in fiji_calculate_sclk_params()
879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
882 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
886 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
888 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
902 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
931 sclk->SclkDid = (uint8_t)dividers in fiji_calculate_sclk_params()
1303 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_acpi_level() local
1423 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_vce_level() local
1462 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_acp_level() local
1558 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_uvd_level() local
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| H A D | vegam_smumgr.c | 725 struct pp_atomctrl_clock_dividers_ai dividers; in vegam_calculate_sclk_params() local
733 /* get the engine clock dividers for this clock value */ in vegam_calculate_sclk_params()
734 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs); in vegam_calculate_sclk_params()
736 sclk_setting->Fcw_int = dividers.usSclk_fcw_int; in vegam_calculate_sclk_params()
737 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac; in vegam_calculate_sclk_params()
738 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int; in vegam_calculate_sclk_params()
739 sclk_setting->PllRange = dividers.ucSclkPllRange; in vegam_calculate_sclk_params()
741 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac; in vegam_calculate_sclk_params()
743 sclk_setting->SSc_En = dividers.ucSscEnable; in vegam_calculate_sclk_params()
744 sclk_setting->Fcw1_int = dividers in vegam_calculate_sclk_params()
1200 struct pp_atomctrl_clock_dividers_vi dividers; vegam_populate_smc_vce_level() local
1313 struct pp_atomctrl_clock_dividers_vi dividers; vegam_populate_smc_uvd_level() local
1932 pp_atomctrl_clock_dividers_vi dividers; vegam_init_smc_table() local
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| H A D | fiji_smumgr.c | 860 struct pp_atomctrl_clock_dividers_vi dividers; in fiji_calculate_sclk_params() local
871 /* get the engine clock dividers for this clock value */ in fiji_calculate_sclk_params()
872 result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock, ÷rs); in fiji_calculate_sclk_params()
875 "Error retrieving Engine Clock dividers from VBIOS.", in fiji_calculate_sclk_params()
880 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()
883 fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF; in fiji_calculate_sclk_params()
887 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
889 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
903 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
932 sclk->SclkDid = (uint8_t)dividers in fiji_calculate_sclk_params()
1304 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_acpi_level() local
1424 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_vce_level() local
1463 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_acp_level() local
1559 struct pp_atomctrl_clock_dividers_vi dividers; fiji_populate_smc_uvd_level() local
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