WREG32_P (reference) in projects: kernel

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Searched refs:WREG32_P (Results 1 - 25 of 136) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	uvd_v1_0.c	227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init() 277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start() 280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start() 281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start() 291 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start() 321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start() 323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start() 342 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start() 344 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start() 355 WREG32_P(UVD_MASTINT_E in uvd_v1_0_start() [all...]
H A D	rs780_dpm.c	202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, in rs780_preset_ranges_slow_clk_fbdiv_en() 205 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, in rs780_preset_ranges_slow_clk_fbdiv_en() 214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv() 217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv() 220 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); in rs780_preset_starting_fbdiv() 261 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 265 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 269 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, in rs780_voltage_scaling_init() 273 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init() 275 WREG32_P(FVTHROT_PWM_CTRL_REG in rs780_voltage_scaling_init() [all...]
H A D	vce_v1_0.c	221 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume() 222 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v1_0_resume() 223 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume() 226 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume() 229 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume() 251 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume() 294 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start() 310 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start() 312 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start() 320 WREG32_P(VCE_SOFT_RESE in vce_v1_0_start() [all...]
H A D	r600_dpm.c	247 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable() 249 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable() 269 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable() 271 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable() 277 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection() 279 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection() 284 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in r600_enable_acpi_pm() 290 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2() 292 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2() 306 WREG32_P(SCLK_PWRMGT_CNT in r600_enable_sclk_control() [all...]
H A D	sumo_dpm.c	91 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable() 93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable() 94 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable() 95 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable() 128 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git() 175 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) \| PGU(u), in sumo_gfx_powergating_initialize() 181 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) \| PGU(u), in sumo_gfx_powergating_initialize() 277 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable() 279 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable() 436 WREG32_P(CG_FFCT_ in sumo_program_tp() [all...]
H A D	vce_v2_0.c	`162 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume() 163 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume() 164 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume() 168 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume() 190 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume() 192 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()`
H A D	r600_hdmi.c	186 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr() 192 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr() 195 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr() 199 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr() 202 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr() 206 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr() 209 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr() 310 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround() 356 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_set_audio_packet() 370 WREG32_P(HDMI0_INFOFRAME_CONTROL in r600_set_audio_packet() [all...]
H A D	rv6xx_dpm.c	317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s() 324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v() 332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum() 335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum() 342 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s() 348 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v() 355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 364 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum() 366 WREG32_P(GENERAL_PWRMG in rv6xx_enable_dynamic_spread_spectrum() [all...]
H A D	dce3_1_afmt.c	`180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr() 183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr() 187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr() 190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr() 194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr() 197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()`
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	uvd_v1_0.c	227 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init() 277 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start() 280 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start() 281 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start() 291 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start() 321 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start() 323 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start() 342 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start() 344 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start() 355 WREG32_P(UVD_MASTINT_E in uvd_v1_0_start() [all...]
H A D	rs780_dpm.c	202 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, in rs780_preset_ranges_slow_clk_fbdiv_en() 205 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, in rs780_preset_ranges_slow_clk_fbdiv_en() 214 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv() 217 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv() 220 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); in rs780_preset_starting_fbdiv() 260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init() 268 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, in rs780_voltage_scaling_init() 272 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init() 274 WREG32_P(FVTHROT_PWM_CTRL_REG in rs780_voltage_scaling_init() [all...]
H A D	vce_v1_0.c	222 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume() 223 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v1_0_resume() 224 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume() 227 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume() 230 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume() 252 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume() 295 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start() 311 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start() 313 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start() 321 WREG32_P(VCE_SOFT_RESE in vce_v1_0_start() [all...]
H A D	r600_dpm.c	247 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable() 249 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable() 269 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable() 271 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable() 277 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection() 279 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection() 284 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in r600_enable_acpi_pm() 290 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2() 292 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2() 306 WREG32_P(SCLK_PWRMGT_CNT in r600_enable_sclk_control() [all...]
H A D	sumo_dpm.c	91 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable() 93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable() 94 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable() 95 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable() 128 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git() 175 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) \| PGU(u), in sumo_gfx_powergating_initialize() 181 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) \| PGU(u), in sumo_gfx_powergating_initialize() 277 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable() 279 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable() 436 WREG32_P(CG_FFCT_ in sumo_program_tp() [all...]
H A D	vce_v2_0.c	`163 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume() 164 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume() 165 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume() 169 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume() 191 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume() 193 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()`
H A D	r600_hdmi.c	187 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr() 193 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr() 196 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr() 200 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr() 203 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr() 207 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr() 210 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr() 311 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround() 357 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_set_audio_packet() 371 WREG32_P(HDMI0_INFOFRAME_CONTROL in r600_set_audio_packet() [all...]
H A D	rv6xx_dpm.c	317 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s() 324 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v() 332 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum() 335 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum() 342 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s() 348 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v() 355 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 357 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum() 364 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum() 366 WREG32_P(GENERAL_PWRMG in rv6xx_enable_dynamic_spread_spectrum() [all...]
H A D	dce3_1_afmt.c	`180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr() 183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr() 187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr() 190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr() 194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr() 197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A D	uvd_v4_2.c	263 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start() 269 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start() 276 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start() 304 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start() 306 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start() 308 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start() 310 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start() 327 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start() 330 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start() 341 WREG32_P(mmUVD_MASTINT_E in uvd_v4_2_start() [all...]
H A D	uvd_v3_1.c	327 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start() 333 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v3_1_start() 340 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start() 368 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start() 370 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start() 372 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start() 374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start() 391 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start() 394 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start() 405 WREG32_P(mmUVD_MASTINT_E in uvd_v3_1_start() [all...]
H A D	vce_v2_0.c	130 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_firmware_loaded() 134 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v2_0_firmware_loaded() 172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume() 173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume() 174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume() 178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_mc_resume() 200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_mc_resume() 236 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start() 265 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start() 291 WREG32_P(mmVCE_LMI_CTRL in vce_v2_0_stop() [all...]
H A D	uvd_v5_0.c	299 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start() 308 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start() 311 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start() 323 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start() 353 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start() 372 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start() 375 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start() 385 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start() 388 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start() 419 WREG32_P(mmUVD_RBC_RB_CNT in uvd_v5_0_start() [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A D	vce_v2_0.c	130 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_firmware_loaded() 134 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v2_0_firmware_loaded() 172 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume() 173 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume() 174 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume() 178 WREG32_P(mmVCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_mc_resume() 200 WREG32_P(mmVCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_mc_resume() 236 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start() 265 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start() 291 WREG32_P(mmVCE_LMI_CTRL in vce_v2_0_stop() [all...]
H A D	uvd_v4_2.c	289 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start() 295 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start() 302 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start() 330 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start() 332 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v4_2_start() 334 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v4_2_start() 336 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start() 353 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start() 356 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start() 367 WREG32_P(mmUVD_MASTINT_E in uvd_v4_2_start() [all...]
H A D	uvd_v3_1.c	331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start() 337 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v3_1_start() 344 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start() 372 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v3_1_start() 374 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); in uvd_v3_1_start() 376 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); in uvd_v3_1_start() 378 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start() 395 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v3_1_start() 398 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v3_1_start() 409 WREG32_P(mmUVD_MASTINT_E in uvd_v3_1_start() [all...]

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