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Searched refs:GCC_NPU_GPLL0_DIV_CLK_SRC (Results 1 - 24 of 24) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h57 #define GCC_NPU_GPLL0_DIV_CLK_SRC 47 macro
H A Dqcom,gcc-sm8150.h56 #define GCC_NPU_GPLL0_DIV_CLK_SRC 46 macro
H A Dqcom,gcc-sm8250.h55 #define GCC_NPU_GPLL0_DIV_CLK_SRC 45 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h57 #define GCC_NPU_GPLL0_DIV_CLK_SRC 47 macro
H A Dqcom,gcc-sm8150.h56 #define GCC_NPU_GPLL0_DIV_CLK_SRC 46 macro
H A Dqcom,gcc-sm8250.h55 #define GCC_NPU_GPLL0_DIV_CLK_SRC 45 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h57 #define GCC_NPU_GPLL0_DIV_CLK_SRC 47 macro
H A Dqcom,gcc-sm8150.h56 #define GCC_NPU_GPLL0_DIV_CLK_SRC 46 macro
H A Dqcom,sm7150-gcc.h52 #define GCC_NPU_GPLL0_DIV_CLK_SRC 40 macro
H A Dqcom,gcc-sc8180x.h54 #define GCC_NPU_GPLL0_DIV_CLK_SRC 44 macro
H A Dqcom,gcc-sm8250.h55 #define GCC_NPU_GPLL0_DIV_CLK_SRC 45 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dqcom,gcc-sc7180.h57 #define GCC_NPU_GPLL0_DIV_CLK_SRC 47 macro
H A Dqcom,gcc-sm8150.h56 #define GCC_NPU_GPLL0_DIV_CLK_SRC 46 macro
H A Dqcom,sm7150-gcc.h52 #define GCC_NPU_GPLL0_DIV_CLK_SRC 40 macro
H A Dqcom,gcc-sc8180x.h54 #define GCC_NPU_GPLL0_DIV_CLK_SRC 44 macro
H A Dqcom,gcc-sm8250.h55 #define GCC_NPU_GPLL0_DIV_CLK_SRC 45 macro
/kernel/linux/linux-5.10/drivers/clk/qcom/
H A Dgcc-sc7180.c2354 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sm8250.c3357 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sm8150.c3518 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
/kernel/linux/linux-6.6/drivers/clk/qcom/
H A Dgcc-sc7180.c2281 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sm7150.c2792 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sm8250.c3354 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sm8150.c3545 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
H A Dgcc-sc8180x.c4291 [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,

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