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Searched refs:shift (Results 1 - 25 of 56) sorted by relevance

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/device/board/hisilicon/hispark_taurus/audio_drivers/soc/src/
H A Dhi3516_dai_ops.c195 uint32_t shift = 0; in SetIISRate() local
206 shift = shiftMax; in SetIISRate()
214 if (itemNum <= shift + 1) { in SetIISRate()
218 regCfgItem[0 + shift].value = mclkSel; in SetIISRate()
219 if (AudioDaiRegUpdate(device, &regCfgItem[0 + shift]) != HDF_SUCCESS) { in SetIISRate()
229 regCfgItem[1 + shift].value = bclkRegVal; in SetIISRate()
230 if (AudioDaiRegUpdate(device, &regCfgItem[1 + shift]) != HDF_SUCCESS) { in SetIISRate()
242 uint32_t shift = 0; in DaiParamsUpdate() local
257 shift = shiftMax; in DaiParamsUpdate()
276 regCfgItem[index2 + shift] in DaiParamsUpdate()
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/device/soc/rockchip/common/sdk_linux/include/linux/
H A Dclk-provider.h527 * @shift: shift to the divider bit field
565 u8 shift; member
600 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
603 unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
612 * @shift: number of bits to shift the bitfield
617 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, lock) \
618 clk_register_divider_table((dev), (name), (parent_name), (flags), (reg), (shift), (width), (clk_divider_flags), \
627 * @shift
759 u8 shift; global() member
920 u8 shift; global() member
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/device/soc/rockchip/common/vendor/drivers/clk/
H A Dclk-dclk-divider.c22 val = readl(divider->reg) >> divider->shift; in clk_dclk_recalc_rate()
58 val = div_mask(divider->width) << (divider->shift + div_shift_width); in clk_dclk_set_rate()
61 val &= ~(div_mask(divider->width) << divider->shift); in clk_dclk_set_rate()
63 val |= value << divider->shift; in clk_dclk_set_rate()
112 mux->shift = mux_shift; in rockchip_clk_register_dclk_branch()
144 div->shift = div_shift; in rockchip_clk_register_dclk_branch()
/device/soc/rockchip/rk3588/kernel/drivers/clk/rockchip/
H A Dclk-dclk-divider.c21 val = readl(divider->reg) >> divider->shift; in clk_dclk_recalc_rate()
58 val = div_mask(divider->width) << (divider->shift + 16); in clk_dclk_set_rate()
61 val &= ~(div_mask(divider->width) << divider->shift); in clk_dclk_set_rate()
63 val |= value << divider->shift; in clk_dclk_set_rate()
119 mux->shift = mux_shift; in rockchip_clk_register_dclk_branch()
149 div->shift = div_shift; in rockchip_clk_register_dclk_branch()
H A Dclk-link.c16 u32 shift; member
30 u32 shift; member
44 .shift = (_shift), \
65 gate->bit_idx = priv->shift; in register_clocks()
161 priv->shift = link_info->shift; in rockchip_clk_link_probe()
H A Dclk.h25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
530 void __iomem *reg, int shift);
555 void __iomem *reg, int shift, int flags,
561 int shift, int width, int mux_flags);
983 #define MMC(_id, cname, pname, offset, shift) \
991 .div_shift = shift, \
/device/soc/rockchip/common/sdk_linux/drivers/clk/rockchip/
H A Dclk-half-divider.c27 val = readl(divider->reg) >> divider->shift; in clk_half_divider_recalc_rate()
115 val = div_mask(divider->width) << (divider->shift + 0x10); in clk_half_divider_set_rate()
118 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
120 val |= value << divider->shift; in clk_half_divider_set_rate()
167 mux->shift = mux_shift; in rockchip_clk_register_halfdiv()
199 div->shift = div_shift; in rockchip_clk_register_halfdiv()
H A Dclk.h25 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
441 void __iomem *reg, int shift);
462 void __iomem *reg, int shift, int flags, spinlock_t *lock);
465 struct regmap *grf, int reg, int shift, int width, int mux_flags);
666 #define MMC(_id, cname, pname, offset, shift) \
669 .num_parents = 1, .muxdiv_offset = (offset), .div_shift = (shift), \
/device/soc/rockchip/common/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_l2_mmu_config.c33 * @shift: The shift of where the field starts in the L2_MMU_CONFIG register
38 u32 value, mask, shift; member
117 mmu_config |= (limit.read.value << limit.read.shift) | in kbase_set_mmu_quirks()
118 (limit.write.value << limit.write.shift); in kbase_set_mmu_quirks()
/device/soc/rockchip/common/vendor/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_l2_mmu_config.c35 * @shift: The shift of where the field starts in the L2_MMU_CONFIG register
40 u32 value, mask, shift; member
104 mmu_config |= (limit.read.value << limit.read.shift) | (limit.write.value << limit.write.shift); in kbase_set_mmu_quirks()
/device/board/hisilicon/hispark_taurus/audio_drivers/codec/hi3516/src/
H A Dhi3516_codec_impl.c62 regAttr->value = (*regValue >> regAttr->shift) & regAttr->mask; in Hi3516CodecRegBitsRead()
85 newValue = regAttr.value << regAttr.shift; in Hi3516CodecRegBitsUpdate()
86 newMask = regAttr.mask << regAttr.shift; in Hi3516CodecRegBitsUpdate()
300 value = value << mixerControl->shift; in AudioUpdateCodecAiaoRegBits()
301 mixerControlMask = mixerControl->mask << mixerControl->shift; in AudioUpdateCodecAiaoRegBits()
/device/soc/rockchip/common/vendor/drivers/rockchip/
H A Dgrf.c15 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
/device/soc/rockchip/common/sdk_linux/drivers/soc/rockchip/
H A Dgrf.c15 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
/device/soc/rockchip/common/vendor/drivers/devfreq/
H A Drockchip_dmc.c199 u32 shift; in px30_de_skew_set_2_reg() local
208 shift = n % ROCKCHIP_DE_SKEW_TWO; in px30_de_skew_set_2_reg()
210 shift = (shift == 0) ? ROCKCHIP_DE_SKEW_FOUR : 0; in px30_de_skew_set_2_reg()
211 tim->ca_skew[offset] &= ~(0xf << shift); in px30_de_skew_set_2_reg()
212 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); in px30_de_skew_set_2_reg()
219 shift = ((n % ROCKCHIP_DE_SKEW_TWENTYONE) % ROCKCHIP_DE_SKEW_TWO); in px30_de_skew_set_2_reg()
221 shift = 0; in px30_de_skew_set_2_reg()
224 shift = (shift in px30_de_skew_set_2_reg()
258 u32 shift; rk3328_de_skew_setting_2_register() local
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/device/soc/rockchip/rk3588/kernel/drivers/devfreq/
H A Drockchip_dmc.c198 u32 shift; in px30_de_skew_set_2_reg() local
207 shift = n % 2; in px30_de_skew_set_2_reg()
209 shift = (shift == 0) ? 4 : 0; in px30_de_skew_set_2_reg()
210 tim->ca_skew[offset] &= ~(0xf << shift); in px30_de_skew_set_2_reg()
211 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift); in px30_de_skew_set_2_reg()
217 shift = ((n % 21) % 2); in px30_de_skew_set_2_reg()
219 shift = 0; in px30_de_skew_set_2_reg()
222 shift = (shift in px30_de_skew_set_2_reg()
254 u32 shift; rk3328_de_skew_setting_2_register() local
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/device/board/hisilicon/hispark_aries/uboot/secureboot_release/ddr_init/boot/
H A D_udivsi3.S27 @ Unless the divisor is very big, shift it up in multiples of
37 @ For very big divisors, we must shift it a bit at a time, or
/device/soc/hisilicon/common/platform/hieth-sf/include/internal/
H A Dhieth_pri.h128 #define MK_BITS(shift, nbits) ((((shift)&0x1F) << 16) | ((nbits)&0x3F))
/device/board/hisilicon/hispark_taurus/uboot/secureboot_release/ddr_init/boot/
H A D_udivsi3.S27 @ Unless the divisor is very big, shift it up in multiples of
37 @ For very big divisors, we must shift it a bit at a time, or
/device/soc/rockchip/common/vendor/drivers/phy/
H A Dphy-rockchip-csi2-dphy-hw.c209 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
213 .offset = (_offset), .mask = BIT(_width) - 1, .shift = (_shift), \
229 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_sys_grf_reg()
231 if (reg->shift) { in write_sys_grf_reg()
239 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_grf_reg()
241 if (reg->shift) { in write_grf_reg()
251 if (reg->shift) { in read_grf_reg()
253 val = (val >> reg->shift) in read_grf_reg()
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H A Dphy-rockchip-csi2-dphy-common.h36 u32 shift; member
/device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-csi2-dphy-hw.c210 #define HIWORD_UPDATE(val, mask, shift) \
211 ((val) << (shift) | (mask) << ((shift) + 16))
214 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
228 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_sys_grf_reg()
230 if (reg->shift) in write_sys_grf_reg()
238 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); in write_grf_reg()
240 if (reg->shift) in write_grf_reg()
249 if (reg->shift) { in read_grf_reg()
251 val = (val >> reg->shift) in read_grf_reg()
[all...]
H A Dphy-rockchip-csi2-dphy-common.h36 u32 shift; member
/device/board/hihope/dayu210/audio_drivers/accessory/es8323/src/
H A Des8323_impl.c193 regAttr->value = (regVal.value >> regAttr->shift) & regAttr->mask; in Es8323RegBitsRead()
203 AUDIO_DRIVER_LOG_DEBUG("mask=0x%x, shift=%d, max=0x%x,min=0x%x, invert=%d", in Es8323RegBitsRead()
204 regAttr->mask, regAttr->shift, regAttr->max, regAttr->min, regAttr->invert); in Es8323RegBitsRead()
222 newValue = regAttr.value << regAttr.shift; in Es8323RegBitsUpdate()
223 newMask = regAttr.mask << regAttr.shift; in Es8323RegBitsUpdate()
238 AUDIO_DRIVER_LOG_DEBUG(" mask=0x%x, shift=%d, max=0x%x, min=0x%x, invert=%d", in Es8323RegBitsUpdate()
239 newMask, regAttr.shift, regAttr.max, regAttr.min, regAttr.invert); in Es8323RegBitsUpdate()
/device/soc/rockchip/rk3588/kernel/drivers/soc/rockchip/
H A Dclk.h25 #define HIWORD_UPDATE(val, mask, shift) \
26 ((val) << (shift) | (mask) << ((shift) + 16))
530 void __iomem *reg, int shift);
555 void __iomem *reg, int shift, int flags,
561 int shift, int width, int mux_flags);
983 #define MMC(_id, cname, pname, offset, shift) \
991 .div_shift = shift, \
/device/soc/hisilicon/hi3861v100/sdk_liteos/platform/os/Huawei_LiteOS/components/lib/libc/musl/include/sys/
H A Dtimex.h26 int shift; member

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