1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Rockchip Generic dmc support.
4 *
5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
7 */
8
9 #include <dt-bindings/clock/rockchip-ddr.h>
10 #include <dt-bindings/soc/rockchip-system-status.h>
11 #include <drm/drm_modeset_lock.h>
12 #include <linux/arm-smccc.h>
13 #include <linux/clk.h>
14 #include <linux/cpu.h>
15 #include <linux/cpufreq.h>
16 #include <linux/delay.h>
17 #include <linux/devfreq.h>
18 #include <linux/devfreq_cooling.h>
19 #include <linux/devfreq-event.h>
20 #include <linux/input.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/of_irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_opp.h>
29 #include <linux/pm_qos.h>
30 #include <linux/regmap.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/rockchip/rockchip_sip.h>
33 #include <linux/rwsem.h>
34 #include <linux/slab.h>
35 #include <linux/string.h>
36 #include <linux/suspend.h>
37 #include <linux/thermal.h>
38
39 #include <soc/rockchip/pm_domains.h>
40 #include <soc/rockchip/rkfb_dmc.h>
41 #include <soc/rockchip/rockchip_dmc.h>
42 #include <soc/rockchip/rockchip_sip.h>
43 #include <soc/rockchip/rockchip_system_monitor.h>
44 #include <soc/rockchip/rockchip-system-status.h>
45 #include <soc/rockchip/rockchip_opp_select.h>
46 #include <soc/rockchip/scpi.h>
47 #include <uapi/drm/drm_mode.h>
48
49 #include "governor.h"
50 #include "rockchip_dmc_timing.h"
51 #include "../soc/rockchip/clk.h"
52 #include "rockchip_drm_drv.h"
53
54 #define system_status_to_dmcfreq(nb) container_of(nb, struct rockchip_dmcfreq, \
55 status_nb)
56 #define reboot_to_dmcfreq(nb) container_of(nb, struct rockchip_dmcfreq, \
57 reboot_nb)
58 #define boost_to_dmcfreq(work) container_of(work, struct rockchip_dmcfreq, \
59 boost_work)
60 #define input_hd_to_dmcfreq(hd) container_of(hd, struct rockchip_dmcfreq, \
61 input_handler)
62
63 #define VIDEO_1080P_SIZE (1920 * 1080)
64 #define FIQ_INIT_HANDLER (0x1)
65 #define FIQ_CPU_TGT_BOOT (0x0) /* to booting cpu */
66 #define FIQ_NUM_FOR_DCF (143) /* NA irq map to fiq for dcf */
67 #define DTS_PAR_OFFSET (4096)
68
69 #define FALLBACK_STATIC_TEMPERATURE 55000
70
71 struct dmc_freq_table {
72 unsigned long freq;
73 unsigned long volt;
74 };
75
76 struct share_params {
77 u32 hz;
78 u32 lcdc_type;
79 u32 vop;
80 u32 vop_dclk_mode;
81 u32 sr_idle_en;
82 u32 addr_mcu_el3;
83 /*
84 * 1: need to wait flag1
85 * 0: never wait flag1
86 */
87 u32 wait_flag1;
88 /*
89 * 1: need to wait flag1
90 * 0: never wait flag1
91 */
92 u32 wait_flag0;
93 u32 complt_hwirq;
94 u32 update_drv_odt_cfg;
95 u32 update_deskew_cfg;
96
97 u32 freq_count;
98 u32 freq_info_mhz[6];
99 /* if need, add parameter after */
100 };
101
102 static struct share_params *ddr_psci_param;
103
104 struct rockchip_dmcfreq_ondemand_data {
105 unsigned int upthreshold;
106 unsigned int downdifferential;
107 };
108
109 struct rockchip_dmcfreq {
110 struct device *dev;
111 struct dmcfreq_common_info info;
112 struct rockchip_dmcfreq_ondemand_data ondemand_data;
113 struct clk *dmc_clk;
114 struct devfreq_event_dev **edev;
115 struct mutex lock; /* serializes access to video_info_list */
116 struct dram_timing *timing;
117 struct regulator *vdd_center;
118 struct notifier_block status_nb;
119 struct list_head video_info_list;
120 struct freq_map_table *cpu_bw_tbl;
121 struct work_struct boost_work;
122 struct input_handler input_handler;
123 struct monitor_dev_info *mdev_info;
124 struct share_params *set_rate_params;
125
126 unsigned long *nocp_bw;
127 unsigned long rate, target_rate;
128 unsigned long volt, target_volt;
129 unsigned long auto_min_rate;
130 unsigned long status_rate;
131 unsigned long normal_rate;
132 unsigned long video_1080p_rate;
133 unsigned long video_4k_rate;
134 unsigned long video_4k_10b_rate;
135 unsigned long performance_rate;
136 unsigned long hdmi_rate;
137 unsigned long idle_rate;
138 unsigned long suspend_rate;
139 unsigned long reboot_rate;
140 unsigned long boost_rate;
141 unsigned long fixed_rate;
142 unsigned long low_power_rate;
143
144 unsigned long freq_count;
145 unsigned long freq_info_rate[6];
146 unsigned long rate_low;
147 unsigned long rate_mid_low;
148 unsigned long rate_mid_high;
149 unsigned long rate_high;
150
151 unsigned int min_cpu_freq;
152 unsigned int system_status_en;
153 unsigned int refresh;
154 int edev_count;
155 int dfi_id;
156 int nocp_cpu_id;
157
158 bool is_fixed;
159 bool is_set_rate_direct;
160
161 struct thermal_cooling_device *devfreq_cooling;
162 u32 static_coefficient;
163 s32 ts[4];
164 struct thermal_zone_device *ddr_tz;
165
166 unsigned int touchboostpulse_duration_val;
167 u64 touchboostpulse_endtime;
168
169 int (*set_auto_self_refresh)(u32 en);
170 };
171
172 static struct pm_qos_request pm_qos;
173
is_dualview(unsigned long status)174 static inline unsigned long is_dualview(unsigned long status)
175 {
176 return (status & SYS_STATUS_LCDC0) && (status & SYS_STATUS_LCDC1);
177 }
178
is_isp(unsigned long status)179 static inline unsigned long is_isp(unsigned long status)
180 {
181 return (status & SYS_STATUS_ISP) ||
182 (status & SYS_STATUS_CIF0) ||
183 (status & SYS_STATUS_CIF1);
184 }
185
186 /*
187 * function: packaging de-skew setting to px30_ddr_dts_config_timing,
188 * px30_ddr_dts_config_timing will pass to trust firmware, and
189 * used direct to set register.
190 * input: de_skew
191 * output: tim
192 */
px30_de_skew_set_2_reg(struct rk3328_ddr_de_skew_setting *de_skew, struct px30_ddr_dts_config_timing *tim)193 static void px30_de_skew_set_2_reg(struct rk3328_ddr_de_skew_setting *de_skew,
194 struct px30_ddr_dts_config_timing *tim)
195 {
196 u32 n;
197 u32 offset;
198 u32 shift;
199
200 memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
201 memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
202 memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
203
204 /* CA de-skew */
205 for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
206 offset = n / 2;
207 shift = n % 2;
208 /* 0 => 4; 1 => 0 */
209 shift = (shift == 0) ? 4 : 0;
210 tim->ca_skew[offset] &= ~(0xf << shift);
211 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
212 }
213
214 /* CS0 data de-skew */
215 for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
216 offset = ((n / 21) * 11) + ((n % 21) / 2);
217 shift = ((n % 21) % 2);
218 if ((n % 21) == 20)
219 shift = 0;
220 else
221 /* 0 => 4; 1 => 0 */
222 shift = (shift == 0) ? 4 : 0;
223 tim->cs0_skew[offset] &= ~(0xf << shift);
224 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
225 }
226
227 /* CS1 data de-skew */
228 for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
229 offset = ((n / 21) * 11) + ((n % 21) / 2);
230 shift = ((n % 21) % 2);
231 if ((n % 21) == 20)
232 shift = 0;
233 else
234 /* 0 => 4; 1 => 0 */
235 shift = (shift == 0) ? 4 : 0;
236 tim->cs1_skew[offset] &= ~(0xf << shift);
237 tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
238 }
239 }
240
241 /*
242 * function: packaging de-skew setting to rk3328_ddr_dts_config_timing,
243 * rk3328_ddr_dts_config_timing will pass to trust firmware, and
244 * used direct to set register.
245 * input: de_skew
246 * output: tim
247 */
248 static void
rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew, struct rk3328_ddr_dts_config_timing *tim)249 rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
250 struct rk3328_ddr_dts_config_timing *tim)
251 {
252 u32 n;
253 u32 offset;
254 u32 shift;
255
256 memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
257 memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
258 memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
259
260 /* CA de-skew */
261 for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
262 offset = n / 2;
263 shift = n % 2;
264 /* 0 => 4; 1 => 0 */
265 shift = (shift == 0) ? 4 : 0;
266 tim->ca_skew[offset] &= ~(0xf << shift);
267 tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
268 }
269
270 /* CS0 data de-skew */
271 for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
272 offset = ((n / 21) * 11) + ((n % 21) / 2);
273 shift = ((n % 21) % 2);
274 if ((n % 21) == 20)
275 shift = 0;
276 else
277 /* 0 => 4; 1 => 0 */
278 shift = (shift == 0) ? 4 : 0;
279 tim->cs0_skew[offset] &= ~(0xf << shift);
280 tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
281 }
282
283 /* CS1 data de-skew */
284 for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
285 offset = ((n / 21) * 11) + ((n % 21) / 2);
286 shift = ((n % 21) % 2);
287 if ((n % 21) == 20)
288 shift = 0;
289 else
290 /* 0 => 4; 1 => 0 */
291 shift = (shift == 0) ? 4 : 0;
292 tim->cs1_skew[offset] &= ~(0xf << shift);
293 tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
294 }
295 }
296
rk_drm_get_lcdc_type(void)297 static int rk_drm_get_lcdc_type(void)
298 {
299 u32 lcdc_type = rockchip_drm_get_sub_dev_type();
300
301 switch (lcdc_type) {
302 case DRM_MODE_CONNECTOR_DPI:
303 case DRM_MODE_CONNECTOR_LVDS:
304 lcdc_type = SCREEN_LVDS;
305 break;
306 case DRM_MODE_CONNECTOR_DisplayPort:
307 lcdc_type = SCREEN_DP;
308 break;
309 case DRM_MODE_CONNECTOR_HDMIA:
310 case DRM_MODE_CONNECTOR_HDMIB:
311 lcdc_type = SCREEN_HDMI;
312 break;
313 case DRM_MODE_CONNECTOR_TV:
314 lcdc_type = SCREEN_TVOUT;
315 break;
316 case DRM_MODE_CONNECTOR_eDP:
317 lcdc_type = SCREEN_EDP;
318 break;
319 case DRM_MODE_CONNECTOR_DSI:
320 lcdc_type = SCREEN_MIPI;
321 break;
322 default:
323 lcdc_type = SCREEN_NULL;
324 break;
325 }
326
327 return lcdc_type;
328 }
329
rockchip_ddr_set_rate(unsigned long target_rate)330 static int rockchip_ddr_set_rate(unsigned long target_rate)
331 {
332 struct arm_smccc_res res;
333
334 ddr_psci_param->hz = target_rate;
335 ddr_psci_param->lcdc_type = rk_drm_get_lcdc_type();
336 ddr_psci_param->wait_flag1 = 1;
337 ddr_psci_param->wait_flag0 = 1;
338
339 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
340 ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE);
341
342 if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT)
343 rockchip_dmcfreq_wait_complete();
344
345 return res.a0;
346 }
347
rockchip_dmcfreq_target(struct device *dev, unsigned long *freq, u32 flags)348 static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
349 u32 flags)
350 {
351 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
352 struct dev_pm_opp *opp;
353 struct cpufreq_policy *policy;
354 unsigned long old_clk_rate = dmcfreq->rate;
355 unsigned long target_volt, target_rate;
356 unsigned int cpu_cur, cpufreq_cur;
357 bool is_cpufreq_changed = false;
358 int err = 0;
359
360 opp = devfreq_recommended_opp(dev, freq, flags);
361 if (IS_ERR(opp)) {
362 dev_err(dev, "Failed to find opp for %lu Hz\n", *freq);
363 return PTR_ERR(opp);
364 }
365 target_volt = dev_pm_opp_get_voltage(opp);
366 dev_pm_opp_put(opp);
367
368 if (dmcfreq->is_set_rate_direct) {
369 target_rate = *freq;
370 } else {
371 target_rate = clk_round_rate(dmcfreq->dmc_clk, *freq);
372 if ((long)target_rate <= 0)
373 target_rate = *freq;
374 }
375
376 if (dmcfreq->rate == target_rate) {
377 if (dmcfreq->volt == target_volt)
378 return 0;
379 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
380 INT_MAX);
381 if (err) {
382 dev_err(dev, "Cannot set voltage %lu uV\n",
383 target_volt);
384 return err;
385 }
386 dmcfreq->volt = target_volt;
387 return 0;
388 } else if (!dmcfreq->volt) {
389 dmcfreq->volt = regulator_get_voltage(dmcfreq->vdd_center);
390 }
391
392 /*
393 * We need to prevent cpu hotplug from happening while a dmc freq rate
394 * change is happening.
395 *
396 * Do this before taking the policy rwsem to avoid deadlocks between the
397 * mutex that is locked/unlocked in cpu_hotplug_disable/enable. And it
398 * can also avoid deadlocks between the mutex that is locked/unlocked
399 * in get/put_online_cpus (such as store_scaling_max_freq()).
400 */
401 get_online_cpus();
402
403 /*
404 * Go to specified cpufreq and block other cpufreq changes since
405 * set_rate needs to complete during vblank.
406 */
407 cpu_cur = raw_smp_processor_id();
408 policy = cpufreq_cpu_get(cpu_cur);
409 if (!policy) {
410 dev_err(dev, "cpu%d policy NULL\n", cpu_cur);
411 goto cpufreq;
412 }
413 down_write(&policy->rwsem);
414 cpufreq_cur = cpufreq_quick_get(cpu_cur);
415
416 /* If we're thermally throttled; don't change; */
417 if (dmcfreq->min_cpu_freq && cpufreq_cur < dmcfreq->min_cpu_freq) {
418 if (policy->max >= dmcfreq->min_cpu_freq) {
419 __cpufreq_driver_target(policy, dmcfreq->min_cpu_freq,
420 CPUFREQ_RELATION_L);
421 is_cpufreq_changed = true;
422 } else {
423 dev_dbg(dev, "CPU may too slow for DMC (%d MHz)\n",
424 policy->max);
425 }
426 }
427
428 /*
429 * If frequency scaling from low to high, adjust voltage first.
430 * If frequency scaling from high to low, adjust frequency first.
431 */
432 if (old_clk_rate < target_rate) {
433 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
434 INT_MAX);
435 if (err) {
436 dev_err(dev, "Cannot set voltage %lu uV\n",
437 target_volt);
438 goto out;
439 }
440 }
441
442 /*
443 * Writer in rwsem may block readers even during its waiting in queue,
444 * and this may lead to a deadlock when the code path takes read sem
445 * twice (e.g. one in vop_lock() and another in rockchip_pmu_lock()).
446 * As a (suboptimal) workaround, let writer to spin until it gets the
447 * lock.
448 */
449 while (!rockchip_dmcfreq_write_trylock())
450 cond_resched();
451 dev_dbg(dev, "%lu-->%lu\n", old_clk_rate, target_rate);
452
453 if (dmcfreq->set_rate_params) {
454 dmcfreq->set_rate_params->lcdc_type = rk_drm_get_lcdc_type();
455 dmcfreq->set_rate_params->wait_flag1 = 1;
456 dmcfreq->set_rate_params->wait_flag0 = 1;
457 }
458
459 if (dmcfreq->is_set_rate_direct)
460 err = rockchip_ddr_set_rate(target_rate);
461 else
462 err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
463
464 rockchip_dmcfreq_write_unlock();
465 if (err) {
466 dev_err(dev, "Cannot set frequency %lu (%d)\n",
467 target_rate, err);
468 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
469 INT_MAX);
470 goto out;
471 }
472
473 /*
474 * Check the dpll rate,
475 * There only two result we will get,
476 * 1. Ddr frequency scaling fail, we still get the old rate.
477 * 2. Ddr frequency scaling sucessful, we get the rate we set.
478 */
479 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
480
481 /* If get the incorrect rate, set voltage to old value. */
482 if (dmcfreq->rate != target_rate) {
483 dev_err(dev, "Get wrong frequency, Request %lu, Current %lu\n",
484 target_rate, dmcfreq->rate);
485 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
486 INT_MAX);
487 goto out;
488 } else if (old_clk_rate > target_rate) {
489 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
490 INT_MAX);
491 if (err) {
492 dev_err(dev, "Cannot set vol %lu uV\n", target_volt);
493 goto out;
494 }
495 }
496
497 if (dmcfreq->info.devfreq) {
498 struct devfreq *devfreq = dmcfreq->info.devfreq;
499
500 devfreq->last_status.current_frequency = *freq;
501 }
502
503 dmcfreq->volt = target_volt;
504 out:
505 if (is_cpufreq_changed)
506 __cpufreq_driver_target(policy, cpufreq_cur,
507 CPUFREQ_RELATION_L);
508 up_write(&policy->rwsem);
509 cpufreq_cpu_put(policy);
510 cpufreq:
511 put_online_cpus();
512 return err;
513 }
514
rockchip_dmcfreq_get_dev_status(struct device *dev, struct devfreq_dev_status *stat)515 static int rockchip_dmcfreq_get_dev_status(struct device *dev,
516 struct devfreq_dev_status *stat)
517 {
518 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
519 struct devfreq_event_data edata;
520 int i, ret = 0;
521
522 if (!dmcfreq->info.auto_freq_en)
523 return -EINVAL;
524
525 for (i = 0; i < dmcfreq->edev_count; i++) {
526 ret = devfreq_event_get_event(dmcfreq->edev[i], &edata);
527 if (ret < 0) {
528 dev_err(dev, "failed to get event %s\n",
529 dmcfreq->edev[i]->desc->name);
530 return ret;
531 }
532 if (i == dmcfreq->dfi_id) {
533 stat->busy_time = edata.load_count;
534 stat->total_time = edata.total_count;
535 } else {
536 dmcfreq->nocp_bw[i] = edata.load_count;
537 }
538 }
539
540 return 0;
541 }
542
rockchip_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)543 static int rockchip_dmcfreq_get_cur_freq(struct device *dev,
544 unsigned long *freq)
545 {
546 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
547
548 *freq = dmcfreq->rate;
549
550 return 0;
551 }
552
553 static struct devfreq_dev_profile rockchip_devfreq_dmc_profile = {
554 .polling_ms = 50,
555 .target = rockchip_dmcfreq_target,
556 .get_dev_status = rockchip_dmcfreq_get_dev_status,
557 .get_cur_freq = rockchip_dmcfreq_get_cur_freq,
558 };
559
560
reset_last_status(struct devfreq *devfreq)561 static inline void reset_last_status(struct devfreq *devfreq)
562 {
563 devfreq->last_status.total_time = 1;
564 devfreq->last_status.busy_time = 1;
565 }
566
of_get_px30_timings(struct device *dev, struct device_node *np, uint32_t *timing)567 static void of_get_px30_timings(struct device *dev,
568 struct device_node *np, uint32_t *timing)
569 {
570 struct device_node *np_tim;
571 u32 *p;
572 struct px30_ddr_dts_config_timing *dts_timing;
573 struct rk3328_ddr_de_skew_setting *de_skew;
574 int ret = 0;
575 u32 i;
576
577 dts_timing =
578 (struct px30_ddr_dts_config_timing *)(timing +
579 DTS_PAR_OFFSET / 4);
580
581 np_tim = of_parse_phandle(np, "ddr_timing", 0);
582 if (!np_tim) {
583 ret = -EINVAL;
584 goto end;
585 }
586 de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
587 if (!de_skew) {
588 ret = -ENOMEM;
589 goto end;
590 }
591 p = (u32 *)dts_timing;
592 for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
593 ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
594 p + i);
595 }
596 p = (u32 *)de_skew->ca_de_skew;
597 for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
598 ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
599 p + i);
600 }
601 p = (u32 *)de_skew->cs0_de_skew;
602 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
603 ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
604 p + i);
605 }
606 p = (u32 *)de_skew->cs1_de_skew;
607 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
608 ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
609 p + i);
610 }
611 if (!ret)
612 px30_de_skew_set_2_reg(de_skew, dts_timing);
613 kfree(de_skew);
614 end:
615 if (!ret) {
616 dts_timing->available = 1;
617 } else {
618 dts_timing->available = 0;
619 dev_err(dev, "of_get_ddr_timings: fail\n");
620 }
621
622 of_node_put(np_tim);
623 }
624
of_get_rk1808_timings(struct device *dev, struct device_node *np, uint32_t *timing)625 static void of_get_rk1808_timings(struct device *dev,
626 struct device_node *np, uint32_t *timing)
627 {
628 struct device_node *np_tim;
629 u32 *p;
630 struct rk1808_ddr_dts_config_timing *dts_timing;
631 int ret = 0;
632 u32 i;
633
634 dts_timing =
635 (struct rk1808_ddr_dts_config_timing *)(timing +
636 DTS_PAR_OFFSET / 4);
637
638 np_tim = of_parse_phandle(np, "ddr_timing", 0);
639 if (!np_tim) {
640 ret = -EINVAL;
641 goto end;
642 }
643
644 p = (u32 *)dts_timing;
645 for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
646 ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
647 p + i);
648 }
649 p = (u32 *)dts_timing->ca_de_skew;
650 for (i = 0; i < ARRAY_SIZE(rk1808_dts_ca_timing); i++) {
651 ret |= of_property_read_u32(np_tim, rk1808_dts_ca_timing[i],
652 p + i);
653 }
654 p = (u32 *)dts_timing->cs0_a_de_skew;
655 for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs0_a_timing); i++) {
656 ret |= of_property_read_u32(np_tim, rk1808_dts_cs0_a_timing[i],
657 p + i);
658 }
659 p = (u32 *)dts_timing->cs0_b_de_skew;
660 for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs0_b_timing); i++) {
661 ret |= of_property_read_u32(np_tim, rk1808_dts_cs0_b_timing[i],
662 p + i);
663 }
664 p = (u32 *)dts_timing->cs1_a_de_skew;
665 for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs1_a_timing); i++) {
666 ret |= of_property_read_u32(np_tim, rk1808_dts_cs1_a_timing[i],
667 p + i);
668 }
669 p = (u32 *)dts_timing->cs1_b_de_skew;
670 for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs1_b_timing); i++) {
671 ret |= of_property_read_u32(np_tim, rk1808_dts_cs1_b_timing[i],
672 p + i);
673 }
674
675 end:
676 if (!ret) {
677 dts_timing->available = 1;
678 } else {
679 dts_timing->available = 0;
680 dev_err(dev, "of_get_ddr_timings: fail\n");
681 }
682
683 of_node_put(np_tim);
684 }
685
of_get_rk3128_timings(struct device *dev, struct device_node *np, uint32_t *timing)686 static void of_get_rk3128_timings(struct device *dev,
687 struct device_node *np, uint32_t *timing)
688 {
689 struct device_node *np_tim;
690 u32 *p;
691 struct rk3128_ddr_dts_config_timing *dts_timing;
692 struct share_params *init_timing;
693 int ret = 0;
694 u32 i;
695
696 init_timing = (struct share_params *)timing;
697
698 if (of_property_read_u32(np, "vop-dclk-mode",
699 &init_timing->vop_dclk_mode))
700 init_timing->vop_dclk_mode = 0;
701
702 p = timing + DTS_PAR_OFFSET / 4;
703 np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
704 if (!np_tim) {
705 ret = -EINVAL;
706 goto end;
707 }
708 for (i = 0; i < ARRAY_SIZE(rk3128_dts_timing); i++) {
709 ret |= of_property_read_u32(np_tim, rk3128_dts_timing[i],
710 p + i);
711 }
712 end:
713 dts_timing =
714 (struct rk3128_ddr_dts_config_timing *)(timing +
715 DTS_PAR_OFFSET / 4);
716 if (!ret) {
717 dts_timing->available = 1;
718 } else {
719 dts_timing->available = 0;
720 dev_err(dev, "of_get_ddr_timings: fail\n");
721 }
722
723 of_node_put(np_tim);
724 }
725
of_get_rk3228_timings(struct device *dev, struct device_node *np, uint32_t *timing)726 static uint32_t of_get_rk3228_timings(struct device *dev,
727 struct device_node *np, uint32_t *timing)
728 {
729 struct device_node *np_tim;
730 u32 *p;
731 int ret = 0;
732 u32 i;
733
734 p = timing + DTS_PAR_OFFSET / 4;
735 np_tim = of_parse_phandle(np, "rockchip,dram_timing", 0);
736 if (!np_tim) {
737 ret = -EINVAL;
738 goto end;
739 }
740 for (i = 0; i < ARRAY_SIZE(rk3228_dts_timing); i++) {
741 ret |= of_property_read_u32(np_tim, rk3228_dts_timing[i],
742 p + i);
743 }
744 end:
745 if (ret)
746 dev_err(dev, "of_get_ddr_timings: fail\n");
747
748 of_node_put(np_tim);
749 return ret;
750 }
751
of_get_rk3288_timings(struct device *dev, struct device_node *np, uint32_t *timing)752 static void of_get_rk3288_timings(struct device *dev,
753 struct device_node *np, uint32_t *timing)
754 {
755 struct device_node *np_tim;
756 u32 *p;
757 struct rk3288_ddr_dts_config_timing *dts_timing;
758 struct share_params *init_timing;
759 int ret = 0;
760 u32 i;
761
762 init_timing = (struct share_params *)timing;
763
764 if (of_property_read_u32(np, "vop-dclk-mode",
765 &init_timing->vop_dclk_mode))
766 init_timing->vop_dclk_mode = 0;
767
768 p = timing + DTS_PAR_OFFSET / 4;
769 np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
770 if (!np_tim) {
771 ret = -EINVAL;
772 goto end;
773 }
774 for (i = 0; i < ARRAY_SIZE(rk3288_dts_timing); i++) {
775 ret |= of_property_read_u32(np_tim, rk3288_dts_timing[i],
776 p + i);
777 }
778 end:
779 dts_timing =
780 (struct rk3288_ddr_dts_config_timing *)(timing +
781 DTS_PAR_OFFSET / 4);
782 if (!ret) {
783 dts_timing->available = 1;
784 } else {
785 dts_timing->available = 0;
786 dev_err(dev, "of_get_ddr_timings: fail\n");
787 }
788
789 of_node_put(np_tim);
790 }
791
of_get_rk3328_timings(struct device *dev, struct device_node *np, uint32_t *timing)792 static void of_get_rk3328_timings(struct device *dev,
793 struct device_node *np, uint32_t *timing)
794 {
795 struct device_node *np_tim;
796 u32 *p;
797 struct rk3328_ddr_dts_config_timing *dts_timing;
798 struct rk3328_ddr_de_skew_setting *de_skew;
799 int ret = 0;
800 u32 i;
801
802 dts_timing =
803 (struct rk3328_ddr_dts_config_timing *)(timing +
804 DTS_PAR_OFFSET / 4);
805
806 np_tim = of_parse_phandle(np, "ddr_timing", 0);
807 if (!np_tim) {
808 ret = -EINVAL;
809 goto end;
810 }
811 de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
812 if (!de_skew) {
813 ret = -ENOMEM;
814 goto end;
815 }
816 p = (u32 *)dts_timing;
817 for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
818 ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
819 p + i);
820 }
821 p = (u32 *)de_skew->ca_de_skew;
822 for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
823 ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
824 p + i);
825 }
826 p = (u32 *)de_skew->cs0_de_skew;
827 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
828 ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
829 p + i);
830 }
831 p = (u32 *)de_skew->cs1_de_skew;
832 for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
833 ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
834 p + i);
835 }
836 if (!ret)
837 rk3328_de_skew_setting_2_register(de_skew, dts_timing);
838 kfree(de_skew);
839 end:
840 if (!ret) {
841 dts_timing->available = 1;
842 } else {
843 dts_timing->available = 0;
844 dev_err(dev, "of_get_ddr_timings: fail\n");
845 }
846
847 of_node_put(np_tim);
848 }
849
of_get_rv1126_timings(struct device *dev, struct device_node *np, uint32_t *timing)850 static void of_get_rv1126_timings(struct device *dev,
851 struct device_node *np, uint32_t *timing)
852 {
853 struct device_node *np_tim;
854 u32 *p;
855 struct rk1808_ddr_dts_config_timing *dts_timing;
856 int ret = 0;
857 u32 i;
858
859 dts_timing =
860 (struct rk1808_ddr_dts_config_timing *)(timing +
861 DTS_PAR_OFFSET / 4);
862
863 np_tim = of_parse_phandle(np, "ddr_timing", 0);
864 if (!np_tim) {
865 ret = -EINVAL;
866 goto end;
867 }
868
869 p = (u32 *)dts_timing;
870 for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
871 ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
872 p + i);
873 }
874 p = (u32 *)dts_timing->ca_de_skew;
875 for (i = 0; i < ARRAY_SIZE(rv1126_dts_ca_timing); i++) {
876 ret |= of_property_read_u32(np_tim, rv1126_dts_ca_timing[i],
877 p + i);
878 }
879 p = (u32 *)dts_timing->cs0_a_de_skew;
880 for (i = 0; i < ARRAY_SIZE(rv1126_dts_cs0_a_timing); i++) {
881 ret |= of_property_read_u32(np_tim, rv1126_dts_cs0_a_timing[i],
882 p + i);
883 }
884 p = (u32 *)dts_timing->cs0_b_de_skew;
885 for (i = 0; i < ARRAY_SIZE(rv1126_dts_cs0_b_timing); i++) {
886 ret |= of_property_read_u32(np_tim, rv1126_dts_cs0_b_timing[i],
887 p + i);
888 }
889 p = (u32 *)dts_timing->cs1_a_de_skew;
890 for (i = 0; i < ARRAY_SIZE(rv1126_dts_cs1_a_timing); i++) {
891 ret |= of_property_read_u32(np_tim, rv1126_dts_cs1_a_timing[i],
892 p + i);
893 }
894 p = (u32 *)dts_timing->cs1_b_de_skew;
895 for (i = 0; i < ARRAY_SIZE(rv1126_dts_cs1_b_timing); i++) {
896 ret |= of_property_read_u32(np_tim, rv1126_dts_cs1_b_timing[i],
897 p + i);
898 }
899
900 end:
901 if (!ret) {
902 dts_timing->available = 1;
903 } else {
904 dts_timing->available = 0;
905 dev_err(dev, "of_get_ddr_timings: fail\n");
906 }
907
908 of_node_put(np_tim);
909 }
910
of_get_rk3368_timings(struct device *dev, struct device_node *np)911 static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
912 struct device_node *np)
913 {
914 struct rk3368_dram_timing *timing = NULL;
915 struct device_node *np_tim;
916 int ret = 0;
917
918 np_tim = of_parse_phandle(np, "ddr_timing", 0);
919 if (np_tim) {
920 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
921 if (!timing)
922 goto err;
923
924 ret |= of_property_read_u32(np_tim, "dram_spd_bin",
925 &timing->dram_spd_bin);
926 ret |= of_property_read_u32(np_tim, "sr_idle",
927 &timing->sr_idle);
928 ret |= of_property_read_u32(np_tim, "pd_idle",
929 &timing->pd_idle);
930 ret |= of_property_read_u32(np_tim, "dram_dll_disb_freq",
931 &timing->dram_dll_dis_freq);
932 ret |= of_property_read_u32(np_tim, "phy_dll_disb_freq",
933 &timing->phy_dll_dis_freq);
934 ret |= of_property_read_u32(np_tim, "dram_odt_disb_freq",
935 &timing->dram_odt_dis_freq);
936 ret |= of_property_read_u32(np_tim, "phy_odt_disb_freq",
937 &timing->phy_odt_dis_freq);
938 ret |= of_property_read_u32(np_tim, "ddr3_drv",
939 &timing->ddr3_drv);
940 ret |= of_property_read_u32(np_tim, "ddr3_odt",
941 &timing->ddr3_odt);
942 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
943 &timing->lpddr3_drv);
944 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
945 &timing->lpddr3_odt);
946 ret |= of_property_read_u32(np_tim, "lpddr2_drv",
947 &timing->lpddr2_drv);
948 ret |= of_property_read_u32(np_tim, "phy_clk_drv",
949 &timing->phy_clk_drv);
950 ret |= of_property_read_u32(np_tim, "phy_cmd_drv",
951 &timing->phy_cmd_drv);
952 ret |= of_property_read_u32(np_tim, "phy_dqs_drv",
953 &timing->phy_dqs_drv);
954 ret |= of_property_read_u32(np_tim, "phy_odt",
955 &timing->phy_odt);
956 ret |= of_property_read_u32(np_tim, "ddr_2t",
957 &timing->ddr_2t);
958 if (ret) {
959 devm_kfree(dev, timing);
960 goto err;
961 }
962 of_node_put(np_tim);
963 return timing;
964 }
965
966 err:
967 if (timing) {
968 devm_kfree(dev, timing);
969 timing = NULL;
970 }
971 of_node_put(np_tim);
972 return timing;
973 }
974
of_get_rk3399_timings(struct device *dev, struct device_node *np)975 static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
976 struct device_node *np)
977 {
978 struct rk3399_dram_timing *timing = NULL;
979 struct device_node *np_tim;
980 int ret;
981
982 np_tim = of_parse_phandle(np, "ddr_timing", 0);
983 if (np_tim) {
984 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
985 if (!timing)
986 goto err;
987
988 ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
989 &timing->ddr3_speed_bin);
990 ret |= of_property_read_u32(np_tim, "pd_idle",
991 &timing->pd_idle);
992 ret |= of_property_read_u32(np_tim, "sr_idle",
993 &timing->sr_idle);
994 ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
995 &timing->sr_mc_gate_idle);
996 ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
997 &timing->srpd_lite_idle);
998 ret |= of_property_read_u32(np_tim, "standby_idle",
999 &timing->standby_idle);
1000 ret |= of_property_read_u32(np_tim, "auto_lp_dis_freq",
1001 &timing->auto_lp_dis_freq);
1002 ret |= of_property_read_u32(np_tim, "ddr3_dll_dis_freq",
1003 &timing->ddr3_dll_dis_freq);
1004 ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
1005 &timing->phy_dll_dis_freq);
1006 ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
1007 &timing->ddr3_odt_dis_freq);
1008 ret |= of_property_read_u32(np_tim, "ddr3_drv",
1009 &timing->ddr3_drv);
1010 ret |= of_property_read_u32(np_tim, "ddr3_odt",
1011 &timing->ddr3_odt);
1012 ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
1013 &timing->phy_ddr3_ca_drv);
1014 ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
1015 &timing->phy_ddr3_dq_drv);
1016 ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
1017 &timing->phy_ddr3_odt);
1018 ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
1019 &timing->lpddr3_odt_dis_freq);
1020 ret |= of_property_read_u32(np_tim, "lpddr3_drv",
1021 &timing->lpddr3_drv);
1022 ret |= of_property_read_u32(np_tim, "lpddr3_odt",
1023 &timing->lpddr3_odt);
1024 ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
1025 &timing->phy_lpddr3_ca_drv);
1026 ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
1027 &timing->phy_lpddr3_dq_drv);
1028 ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
1029 &timing->phy_lpddr3_odt);
1030 ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
1031 &timing->lpddr4_odt_dis_freq);
1032 ret |= of_property_read_u32(np_tim, "lpddr4_drv",
1033 &timing->lpddr4_drv);
1034 ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
1035 &timing->lpddr4_dq_odt);
1036 ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
1037 &timing->lpddr4_ca_odt);
1038 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
1039 &timing->phy_lpddr4_ca_drv);
1040 ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
1041 &timing->phy_lpddr4_ck_cs_drv);
1042 ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
1043 &timing->phy_lpddr4_dq_drv);
1044 ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
1045 &timing->phy_lpddr4_odt);
1046 if (ret) {
1047 devm_kfree(dev, timing);
1048 goto err;
1049 }
1050 of_node_put(np_tim);
1051 return timing;
1052 }
1053
1054 err:
1055 if (timing) {
1056 devm_kfree(dev, timing);
1057 timing = NULL;
1058 }
1059 of_node_put(np_tim);
1060 return timing;
1061 }
1062
rockchip_ddr_set_auto_self_refresh(uint32_t en)1063 static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
1064 {
1065 struct arm_smccc_res res;
1066
1067 ddr_psci_param->sr_idle_en = en;
1068 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1069 ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR);
1070
1071 return res.a0;
1072 }
1073
1074 struct dmcfreq_wait_ctrl_t {
1075 wait_queue_head_t wait_wq;
1076 int complt_irq;
1077 int wait_flag;
1078 int wait_en;
1079 int wait_time_out_ms;
1080 int dcf_en;
1081 struct regmap *regmap_dcf;
1082 };
1083
1084 static struct dmcfreq_wait_ctrl_t wait_ctrl;
1085
wait_complete_irq(int irqno, void *dev_id)1086 static irqreturn_t wait_complete_irq(int irqno, void *dev_id)
1087 {
1088 struct dmcfreq_wait_ctrl_t *ctrl = dev_id;
1089
1090 ctrl->wait_flag = 0;
1091 wake_up(&ctrl->wait_wq);
1092 return IRQ_HANDLED;
1093 }
1094
wait_dcf_complete_irq(int irqno, void *dev_id)1095 static irqreturn_t wait_dcf_complete_irq(int irqno, void *dev_id)
1096 {
1097 struct arm_smccc_res res;
1098 struct dmcfreq_wait_ctrl_t *ctrl = dev_id;
1099
1100 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1101 ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE);
1102 if (res.a0)
1103 pr_err("%s: dram post set rate error:%lx\n", __func__, res.a0);
1104
1105 ctrl->wait_flag = 0;
1106 wake_up(&ctrl->wait_wq);
1107 return IRQ_HANDLED;
1108 }
1109
rockchip_dmcfreq_wait_complete(void)1110 int rockchip_dmcfreq_wait_complete(void)
1111 {
1112 struct arm_smccc_res res;
1113
1114 if (!wait_ctrl.wait_en) {
1115 pr_err("%s: Do not support time out!\n", __func__);
1116 return 0;
1117 }
1118 wait_ctrl.wait_flag = -1;
1119
1120 enable_irq(wait_ctrl.complt_irq);
1121 /*
1122 * CPUs only enter WFI when idle to make sure that
1123 * FIQn can quick response.
1124 */
1125 cpu_latency_qos_update_request(&pm_qos, 0);
1126
1127 if (wait_ctrl.dcf_en == 1) {
1128 /* start dcf */
1129 regmap_update_bits(wait_ctrl.regmap_dcf, 0x0, 0x1, 0x1);
1130 } else if (wait_ctrl.dcf_en == 2) {
1131 res = sip_smc_dram(0, 0, ROCKCHIP_SIP_CONFIG_MCU_START);
1132 if (res.a0) {
1133 pr_err("rockchip_sip_config_mcu_start error:%lx\n", res.a0);
1134 return -ENOMEM;
1135 }
1136 }
1137
1138 wait_event_timeout(wait_ctrl.wait_wq, (wait_ctrl.wait_flag == 0),
1139 msecs_to_jiffies(wait_ctrl.wait_time_out_ms));
1140
1141 cpu_latency_qos_update_request(&pm_qos, PM_QOS_DEFAULT_VALUE);
1142 disable_irq(wait_ctrl.complt_irq);
1143
1144 return 0;
1145 }
1146
rockchip_get_freq_info(struct rockchip_dmcfreq *dmcfreq)1147 static __maybe_unused int rockchip_get_freq_info(struct rockchip_dmcfreq *dmcfreq)
1148 {
1149 struct arm_smccc_res res;
1150 struct dev_pm_opp *opp;
1151 struct dmc_freq_table *freq_table;
1152 unsigned long rate;
1153 int i, j, count, ret = 0;
1154
1155 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1156 ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO);
1157 if (res.a0) {
1158 dev_err(dmcfreq->dev, "rockchip_sip_config_dram_get_freq_info error:%lx\n",
1159 res.a0);
1160 return -ENOMEM;
1161 }
1162
1163 if (ddr_psci_param->freq_count == 0 || ddr_psci_param->freq_count > 6) {
1164 dev_err(dmcfreq->dev, "it is no available frequencies!\n");
1165 return -EPERM;
1166 }
1167
1168 for (i = 0; i < ddr_psci_param->freq_count; i++)
1169 dmcfreq->freq_info_rate[i] = ddr_psci_param->freq_info_mhz[i] * 1000000;
1170 dmcfreq->freq_count = ddr_psci_param->freq_count;
1171
1172 /* update dmc_opp_table */
1173 count = dev_pm_opp_get_opp_count(dmcfreq->dev);
1174 if (count <= 0) {
1175 ret = count ? count : -ENODATA;
1176 return ret;
1177 }
1178
1179 freq_table = kmalloc(sizeof(struct dmc_freq_table) * count, GFP_KERNEL);
1180 for (i = 0, rate = 0; i < count; i++, rate++) {
1181 /* find next rate */
1182 opp = dev_pm_opp_find_freq_ceil(dmcfreq->dev, &rate);
1183 if (IS_ERR(opp)) {
1184 ret = PTR_ERR(opp);
1185 dev_err(dmcfreq->dev, "failed to find OPP for freq %lu.\n", rate);
1186 goto out;
1187 }
1188 freq_table[i].freq = rate;
1189 freq_table[i].volt = dev_pm_opp_get_voltage(opp);
1190 dev_pm_opp_put(opp);
1191
1192 for (j = 0; j < dmcfreq->freq_count; j++) {
1193 if (rate == dmcfreq->freq_info_rate[j])
1194 break;
1195 }
1196 if (j == dmcfreq->freq_count)
1197 dev_pm_opp_remove(dmcfreq->dev, rate);
1198 }
1199
1200 for (i = 0; i < dmcfreq->freq_count; i++) {
1201 for (j = 0; j < count; j++) {
1202 if (dmcfreq->freq_info_rate[i] == freq_table[j].freq) {
1203 break;
1204 } else if (dmcfreq->freq_info_rate[i] < freq_table[j].freq) {
1205 dev_pm_opp_add(dmcfreq->dev, dmcfreq->freq_info_rate[i],
1206 freq_table[j].volt);
1207 break;
1208 }
1209 }
1210 if (j == count) {
1211 dev_err(dmcfreq->dev, "failed to match dmc_opp_table for %ld\n",
1212 dmcfreq->freq_info_rate[i]);
1213 if (i == 0)
1214 ret = -EPERM;
1215 else
1216 dmcfreq->freq_count = i;
1217 goto out;
1218 }
1219 }
1220
1221 out:
1222 kfree(freq_table);
1223 return ret;
1224 }
1225
px30_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1226 static __maybe_unused int px30_dmc_init(struct platform_device *pdev,
1227 struct rockchip_dmcfreq *dmcfreq)
1228 {
1229 struct arm_smccc_res res;
1230 u32 size;
1231 int ret;
1232 int complt_irq;
1233 u32 complt_hwirq;
1234 struct irq_data *complt_irq_data;
1235
1236 res = sip_smc_dram(0, 0,
1237 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1238 dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
1239 if (res.a0 || res.a1 < 0x103) {
1240 dev_err(&pdev->dev,
1241 "trusted firmware need to update or is invalid!\n");
1242 return -ENXIO;
1243 }
1244
1245 dev_notice(&pdev->dev, "read tf version 0x%lx!\n", res.a1);
1246
1247 /*
1248 * first 4KB is used for interface parameters
1249 * after 4KB * N is dts parameters
1250 */
1251 size = sizeof(struct px30_ddr_dts_config_timing);
1252 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
1253 SHARE_PAGE_TYPE_DDR);
1254 if (res.a0 != 0) {
1255 dev_err(&pdev->dev, "no ATF memory for init\n");
1256 return -ENOMEM;
1257 }
1258 ddr_psci_param = (struct share_params *)res.a1;
1259 of_get_px30_timings(&pdev->dev, pdev->dev.of_node,
1260 (uint32_t *)ddr_psci_param);
1261
1262 init_waitqueue_head(&wait_ctrl.wait_wq);
1263 wait_ctrl.wait_en = 1;
1264 wait_ctrl.wait_time_out_ms = 17 * 5;
1265
1266 complt_irq = platform_get_irq_byname(pdev, "complete_irq");
1267 if (complt_irq < 0) {
1268 dev_err(&pdev->dev, "no IRQ for complete_irq: %d\n",
1269 complt_irq);
1270 return complt_irq;
1271 }
1272 wait_ctrl.complt_irq = complt_irq;
1273
1274 ret = devm_request_irq(&pdev->dev, complt_irq, wait_complete_irq,
1275 0, dev_name(&pdev->dev), &wait_ctrl);
1276 if (ret < 0) {
1277 dev_err(&pdev->dev, "cannot request complete_irq\n");
1278 return ret;
1279 }
1280 disable_irq(complt_irq);
1281
1282 complt_irq_data = irq_get_irq_data(complt_irq);
1283 complt_hwirq = irqd_to_hwirq(complt_irq_data);
1284 ddr_psci_param->complt_hwirq = complt_hwirq;
1285
1286 dmcfreq->set_rate_params = ddr_psci_param;
1287 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1288 rockchip_set_ddrclk_dmcfreq_wait_complete(rockchip_dmcfreq_wait_complete);
1289
1290 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1291 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1292 if (res.a0) {
1293 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1294 res.a0);
1295 return -ENOMEM;
1296 }
1297
1298 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1299
1300 return 0;
1301 }
1302
rk1808_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1303 static __maybe_unused int rk1808_dmc_init(struct platform_device *pdev,
1304 struct rockchip_dmcfreq *dmcfreq)
1305 {
1306 struct arm_smccc_res res;
1307 u32 size;
1308 int ret;
1309 int complt_irq;
1310 struct device_node *node;
1311
1312 res = sip_smc_dram(0, 0,
1313 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1314 dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
1315 if (res.a0 || res.a1 < 0x101) {
1316 dev_err(&pdev->dev,
1317 "trusted firmware need to update or is invalid!\n");
1318 return -ENXIO;
1319 }
1320
1321 /*
1322 * first 4KB is used for interface parameters
1323 * after 4KB * N is dts parameters
1324 */
1325 size = sizeof(struct rk1808_ddr_dts_config_timing);
1326 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
1327 SHARE_PAGE_TYPE_DDR);
1328 if (res.a0 != 0) {
1329 dev_err(&pdev->dev, "no ATF memory for init\n");
1330 return -ENOMEM;
1331 }
1332 ddr_psci_param = (struct share_params *)res.a1;
1333 of_get_rk1808_timings(&pdev->dev, pdev->dev.of_node,
1334 (uint32_t *)ddr_psci_param);
1335
1336 /* enable start dcf in kernel after dcf ready */
1337 node = of_parse_phandle(pdev->dev.of_node, "dcf_reg", 0);
1338 wait_ctrl.regmap_dcf = syscon_node_to_regmap(node);
1339 if (IS_ERR(wait_ctrl.regmap_dcf))
1340 return PTR_ERR(wait_ctrl.regmap_dcf);
1341 wait_ctrl.dcf_en = 1;
1342
1343 init_waitqueue_head(&wait_ctrl.wait_wq);
1344 wait_ctrl.wait_en = 1;
1345 wait_ctrl.wait_time_out_ms = 17 * 5;
1346
1347 complt_irq = platform_get_irq_byname(pdev, "complete_irq");
1348 if (complt_irq < 0) {
1349 dev_err(&pdev->dev, "no IRQ for complete_irq: %d\n",
1350 complt_irq);
1351 return complt_irq;
1352 }
1353 wait_ctrl.complt_irq = complt_irq;
1354
1355 ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
1356 0, dev_name(&pdev->dev), &wait_ctrl);
1357 if (ret < 0) {
1358 dev_err(&pdev->dev, "cannot request complete_irq\n");
1359 return ret;
1360 }
1361 disable_irq(complt_irq);
1362
1363 dmcfreq->set_rate_params = ddr_psci_param;
1364 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1365 rockchip_set_ddrclk_dmcfreq_wait_complete(rockchip_dmcfreq_wait_complete);
1366
1367 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1368 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1369 if (res.a0) {
1370 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1371 res.a0);
1372 return -ENOMEM;
1373 }
1374
1375 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1376
1377 return 0;
1378 }
1379
rk3128_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1380 static __maybe_unused int rk3128_dmc_init(struct platform_device *pdev,
1381 struct rockchip_dmcfreq *dmcfreq)
1382 {
1383 struct arm_smccc_res res;
1384
1385 res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
1386 struct rk3128_ddr_dts_config_timing),
1387 4096) + 1, SHARE_PAGE_TYPE_DDR);
1388 if (res.a0) {
1389 dev_err(&pdev->dev, "no ATF memory for init\n");
1390 return -ENOMEM;
1391 }
1392 ddr_psci_param = (struct share_params *)res.a1;
1393 of_get_rk3128_timings(&pdev->dev, pdev->dev.of_node,
1394 (uint32_t *)ddr_psci_param);
1395
1396 ddr_psci_param->hz = 0;
1397 ddr_psci_param->lcdc_type = rk_drm_get_lcdc_type();
1398
1399 dmcfreq->set_rate_params = ddr_psci_param;
1400 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1401
1402 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1403 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1404
1405 if (res.a0) {
1406 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1407 res.a0);
1408 return -ENOMEM;
1409 }
1410
1411 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1412
1413 return 0;
1414 }
1415
rk3228_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1416 static __maybe_unused int rk3228_dmc_init(struct platform_device *pdev,
1417 struct rockchip_dmcfreq *dmcfreq)
1418 {
1419 struct arm_smccc_res res;
1420
1421 res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
1422 struct rk3228_ddr_dts_config_timing),
1423 4096) + 1, SHARE_PAGE_TYPE_DDR);
1424 if (res.a0) {
1425 dev_err(&pdev->dev, "no ATF memory for init\n");
1426 return -ENOMEM;
1427 }
1428
1429 ddr_psci_param = (struct share_params *)res.a1;
1430 if (of_get_rk3228_timings(&pdev->dev, pdev->dev.of_node,
1431 (uint32_t *)ddr_psci_param))
1432 return -ENOMEM;
1433
1434 ddr_psci_param->hz = 0;
1435
1436 dmcfreq->set_rate_params = ddr_psci_param;
1437 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1438
1439 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1440 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1441
1442 if (res.a0) {
1443 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1444 res.a0);
1445 return -ENOMEM;
1446 }
1447
1448 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1449
1450 return 0;
1451 }
1452
rk3288_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1453 static __maybe_unused int rk3288_dmc_init(struct platform_device *pdev,
1454 struct rockchip_dmcfreq *dmcfreq)
1455 {
1456 struct device *dev = &pdev->dev;
1457 struct clk *pclk_phy, *pclk_upctl, *dmc_clk;
1458 struct arm_smccc_res res;
1459 int ret;
1460
1461 dmc_clk = devm_clk_get(dev, "dmc_clk");
1462 if (IS_ERR(dmc_clk)) {
1463 dev_err(dev, "Cannot get the clk dmc_clk\n");
1464 return PTR_ERR(dmc_clk);
1465 }
1466 ret = clk_prepare_enable(dmc_clk);
1467 if (ret < 0) {
1468 dev_err(dev, "failed to prepare/enable dmc_clk\n");
1469 return ret;
1470 }
1471
1472 pclk_phy = devm_clk_get(dev, "pclk_phy0");
1473 if (IS_ERR(pclk_phy)) {
1474 dev_err(dev, "Cannot get the clk pclk_phy0\n");
1475 return PTR_ERR(pclk_phy);
1476 }
1477 ret = clk_prepare_enable(pclk_phy);
1478 if (ret < 0) {
1479 dev_err(dev, "failed to prepare/enable pclk_phy0\n");
1480 return ret;
1481 }
1482 pclk_upctl = devm_clk_get(dev, "pclk_upctl0");
1483 if (IS_ERR(pclk_upctl)) {
1484 dev_err(dev, "Cannot get the clk pclk_upctl0\n");
1485 return PTR_ERR(pclk_upctl);
1486 }
1487 ret = clk_prepare_enable(pclk_upctl);
1488 if (ret < 0) {
1489 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
1490 return ret;
1491 }
1492
1493 pclk_phy = devm_clk_get(dev, "pclk_phy1");
1494 if (IS_ERR(pclk_phy)) {
1495 dev_err(dev, "Cannot get the clk pclk_phy1\n");
1496 return PTR_ERR(pclk_phy);
1497 }
1498 ret = clk_prepare_enable(pclk_phy);
1499 if (ret < 0) {
1500 dev_err(dev, "failed to prepare/enable pclk_phy1\n");
1501 return ret;
1502 }
1503 pclk_upctl = devm_clk_get(dev, "pclk_upctl1");
1504 if (IS_ERR(pclk_upctl)) {
1505 dev_err(dev, "Cannot get the clk pclk_upctl1\n");
1506 return PTR_ERR(pclk_upctl);
1507 }
1508 ret = clk_prepare_enable(pclk_upctl);
1509 if (ret < 0) {
1510 dev_err(dev, "failed to prepare/enable pclk_upctl1\n");
1511 return ret;
1512 }
1513
1514 res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
1515 struct rk3288_ddr_dts_config_timing),
1516 4096) + 1, SHARE_PAGE_TYPE_DDR);
1517 if (res.a0) {
1518 dev_err(&pdev->dev, "no ATF memory for init\n");
1519 return -ENOMEM;
1520 }
1521
1522 ddr_psci_param = (struct share_params *)res.a1;
1523 of_get_rk3288_timings(&pdev->dev, pdev->dev.of_node,
1524 (uint32_t *)ddr_psci_param);
1525
1526 ddr_psci_param->hz = 0;
1527 ddr_psci_param->lcdc_type = rk_drm_get_lcdc_type();
1528
1529 dmcfreq->set_rate_params = ddr_psci_param;
1530 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1531
1532 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1533 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1534
1535 if (res.a0) {
1536 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1537 res.a0);
1538 return -ENOMEM;
1539 }
1540
1541 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1542
1543 return 0;
1544 }
1545
rk3328_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1546 static __maybe_unused int rk3328_dmc_init(struct platform_device *pdev,
1547 struct rockchip_dmcfreq *dmcfreq)
1548 {
1549 struct arm_smccc_res res;
1550 u32 size;
1551
1552 res = sip_smc_dram(0, 0,
1553 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1554 dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
1555 if (res.a0 || (res.a1 < 0x101)) {
1556 dev_err(&pdev->dev,
1557 "trusted firmware need to update or is invalid!\n");
1558 return -ENXIO;
1559 }
1560
1561 dev_notice(&pdev->dev, "read tf version 0x%lx!\n", res.a1);
1562
1563 /*
1564 * first 4KB is used for interface parameters
1565 * after 4KB * N is dts parameters
1566 */
1567 size = sizeof(struct rk3328_ddr_dts_config_timing);
1568 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
1569 SHARE_PAGE_TYPE_DDR);
1570 if (res.a0 != 0) {
1571 dev_err(&pdev->dev, "no ATF memory for init\n");
1572 return -ENOMEM;
1573 }
1574 ddr_psci_param = (struct share_params *)res.a1;
1575 of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
1576 (uint32_t *)ddr_psci_param);
1577
1578 dmcfreq->set_rate_params = ddr_psci_param;
1579 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1580
1581 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1582 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1583 if (res.a0) {
1584 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1585 res.a0);
1586 return -ENOMEM;
1587 }
1588
1589 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1590
1591 return 0;
1592 }
1593
rk3368_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1594 static __maybe_unused int rk3368_dmc_init(struct platform_device *pdev,
1595 struct rockchip_dmcfreq *dmcfreq)
1596 {
1597 struct device *dev = &pdev->dev;
1598 struct device_node *np = pdev->dev.of_node;
1599 struct arm_smccc_res res;
1600 struct rk3368_dram_timing *dram_timing;
1601 struct clk *pclk_phy, *pclk_upctl;
1602 int ret;
1603 u32 dram_spd_bin;
1604 u32 addr_mcu_el3;
1605 u32 dclk_mode;
1606 u32 lcdc_type;
1607
1608 pclk_phy = devm_clk_get(dev, "pclk_phy");
1609 if (IS_ERR(pclk_phy)) {
1610 dev_err(dev, "Cannot get the clk pclk_phy\n");
1611 return PTR_ERR(pclk_phy);
1612 }
1613 ret = clk_prepare_enable(pclk_phy);
1614 if (ret < 0) {
1615 dev_err(dev, "failed to prepare/enable pclk_phy\n");
1616 return ret;
1617 }
1618 pclk_upctl = devm_clk_get(dev, "pclk_upctl");
1619 if (IS_ERR(pclk_upctl)) {
1620 dev_err(dev, "Cannot get the clk pclk_upctl\n");
1621 return PTR_ERR(pclk_upctl);
1622 }
1623 ret = clk_prepare_enable(pclk_upctl);
1624 if (ret < 0) {
1625 dev_err(dev, "failed to prepare/enable pclk_upctl\n");
1626 return ret;
1627 }
1628
1629 /*
1630 * Get dram timing and pass it to arm trust firmware,
1631 * the dram drvier in arm trust firmware will get these
1632 * timing and to do dram initial.
1633 */
1634 dram_timing = of_get_rk3368_timings(dev, np);
1635 if (dram_timing) {
1636 dram_spd_bin = dram_timing->dram_spd_bin;
1637 if (scpi_ddr_send_timing((u32 *)dram_timing,
1638 sizeof(struct rk3368_dram_timing)))
1639 dev_err(dev, "send ddr timing timeout\n");
1640 } else {
1641 dev_err(dev, "get ddr timing from dts error\n");
1642 dram_spd_bin = DDR3_DEFAULT;
1643 }
1644
1645 res = sip_smc_mcu_el3fiq(FIQ_INIT_HANDLER,
1646 FIQ_NUM_FOR_DCF,
1647 FIQ_CPU_TGT_BOOT);
1648 if ((res.a0) || (res.a1 == 0) || (res.a1 > 0x80000))
1649 dev_err(dev, "Trust version error, pls check trust version\n");
1650 addr_mcu_el3 = res.a1;
1651
1652 if (of_property_read_u32(np, "vop-dclk-mode", &dclk_mode) == 0)
1653 scpi_ddr_dclk_mode(dclk_mode);
1654
1655 dmcfreq->set_rate_params =
1656 devm_kzalloc(dev, sizeof(struct share_params), GFP_KERNEL);
1657 if (!dmcfreq->set_rate_params)
1658 return -ENOMEM;
1659 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1660
1661 lcdc_type = rk_drm_get_lcdc_type();
1662
1663 if (scpi_ddr_init(dram_spd_bin, 0, lcdc_type,
1664 addr_mcu_el3))
1665 dev_err(dev, "ddr init error\n");
1666 else
1667 dev_dbg(dev, ("%s out\n"), __func__);
1668
1669 dmcfreq->set_auto_self_refresh = scpi_ddr_set_auto_self_refresh;
1670
1671 return 0;
1672 }
1673
rk3399_set_msch_readlatency(unsigned int readlatency)1674 static int rk3399_set_msch_readlatency(unsigned int readlatency)
1675 {
1676 struct arm_smccc_res res;
1677
1678 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, readlatency, 0,
1679 ROCKCHIP_SIP_CONFIG_DRAM_SET_MSCH_RL,
1680 0, 0, 0, 0, &res);
1681
1682 return res.a0;
1683 }
1684
rk3399_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1685 static __maybe_unused int rk3399_dmc_init(struct platform_device *pdev,
1686 struct rockchip_dmcfreq *dmcfreq)
1687 {
1688 struct device *dev = &pdev->dev;
1689 struct device_node *np = pdev->dev.of_node;
1690 struct arm_smccc_res res;
1691 struct rk3399_dram_timing *dram_timing;
1692 int index, size;
1693 u32 *timing;
1694
1695 /*
1696 * Get dram timing and pass it to arm trust firmware,
1697 * the dram drvier in arm trust firmware will get these
1698 * timing and to do dram initial.
1699 */
1700 dram_timing = of_get_rk3399_timings(dev, np);
1701 if (dram_timing) {
1702 timing = (u32 *)dram_timing;
1703 size = sizeof(struct rk3399_dram_timing) / 4;
1704 for (index = 0; index < size; index++) {
1705 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
1706 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
1707 0, 0, 0, 0, &res);
1708 if (res.a0) {
1709 dev_err(dev, "Failed to set dram param: %ld\n",
1710 res.a0);
1711 return -EINVAL;
1712 }
1713 }
1714 }
1715
1716 dmcfreq->set_rate_params =
1717 devm_kzalloc(dev, sizeof(struct share_params), GFP_KERNEL);
1718 if (!dmcfreq->set_rate_params)
1719 return -ENOMEM;
1720 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1721
1722 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
1723 ROCKCHIP_SIP_CONFIG_DRAM_INIT,
1724 0, 0, 0, 0, &res);
1725
1726 dmcfreq->info.set_msch_readlatency = rk3399_set_msch_readlatency;
1727
1728 return 0;
1729 }
1730
rk3568_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1731 static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
1732 struct rockchip_dmcfreq *dmcfreq)
1733 {
1734 struct arm_smccc_res res;
1735 int ret;
1736 int complt_irq;
1737
1738 res = sip_smc_dram(0, 0,
1739 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1740 dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
1741 if (res.a0 || res.a1 < 0x101) {
1742 dev_err(&pdev->dev, "trusted firmware need update to V1.01 and above.\n");
1743 return -ENXIO;
1744 }
1745
1746 /*
1747 * first 4KB is used for interface parameters
1748 * after 4KB is dts parameters
1749 * request share memory size 4KB * 2
1750 */
1751 res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_DDR);
1752 if (res.a0 != 0) {
1753 dev_err(&pdev->dev, "no ATF memory for init\n");
1754 return -ENOMEM;
1755 }
1756 ddr_psci_param = (struct share_params *)res.a1;
1757 /* Clear ddr_psci_param, size is 4KB * 2 */
1758 memset_io(ddr_psci_param, 0x0, 4096 * 2);
1759
1760 /* start mcu with sip_smc_dram */
1761 wait_ctrl.dcf_en = 2;
1762
1763 init_waitqueue_head(&wait_ctrl.wait_wq);
1764 wait_ctrl.wait_en = 1;
1765 wait_ctrl.wait_time_out_ms = 17 * 5;
1766
1767 complt_irq = platform_get_irq_byname(pdev, "complete");
1768 if (complt_irq < 0) {
1769 dev_err(&pdev->dev, "no IRQ for complt_irq: %d\n",
1770 complt_irq);
1771 return complt_irq;
1772 }
1773 wait_ctrl.complt_irq = complt_irq;
1774
1775 ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
1776 0, dev_name(&pdev->dev), &wait_ctrl);
1777 if (ret < 0) {
1778 dev_err(&pdev->dev, "cannot request complt_irq\n");
1779 return ret;
1780 }
1781 disable_irq(complt_irq);
1782
1783 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1784 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1785 if (res.a0) {
1786 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1787 res.a0);
1788 return -ENOMEM;
1789 }
1790
1791 ret = rockchip_get_freq_info(dmcfreq);
1792 if (ret < 0) {
1793 dev_err(&pdev->dev, "cannot get frequency info\n");
1794 return ret;
1795 }
1796 dmcfreq->is_set_rate_direct = true;
1797
1798 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1799
1800 return 0;
1801 }
1802
rk3588_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1803 static __maybe_unused int rk3588_dmc_init(struct platform_device *pdev,
1804 struct rockchip_dmcfreq *dmcfreq)
1805 {
1806 struct arm_smccc_res res;
1807 int ret;
1808 int complt_irq;
1809
1810 res = sip_smc_dram(0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1811 dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
1812 if (res.a0) {
1813 dev_err(&pdev->dev, "trusted firmware unsupported, please update.\n");
1814 return -ENXIO;
1815 }
1816
1817 /*
1818 * first 4KB is used for interface parameters
1819 * after 4KB is dts parameters
1820 * request share memory size 4KB * 2
1821 */
1822 res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_DDR);
1823 if (res.a0 != 0) {
1824 dev_err(&pdev->dev, "no ATF memory for init\n");
1825 return -ENOMEM;
1826 }
1827 ddr_psci_param = (struct share_params *)res.a1;
1828 /* Clear ddr_psci_param, size is 4KB * 2 */
1829 memset_io(ddr_psci_param, 0x0, 4096 * 2);
1830
1831 /* start mcu with sip_smc_dram */
1832 wait_ctrl.dcf_en = 2;
1833
1834 init_waitqueue_head(&wait_ctrl.wait_wq);
1835 wait_ctrl.wait_en = 1;
1836 wait_ctrl.wait_time_out_ms = 17 * 5;
1837
1838 complt_irq = platform_get_irq_byname(pdev, "complete");
1839 if (complt_irq < 0) {
1840 dev_err(&pdev->dev, "no IRQ for complt_irq: %d\n", complt_irq);
1841 return complt_irq;
1842 }
1843 wait_ctrl.complt_irq = complt_irq;
1844
1845 ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
1846 0, dev_name(&pdev->dev), &wait_ctrl);
1847 if (ret < 0) {
1848 dev_err(&pdev->dev, "cannot request complt_irq\n");
1849 return ret;
1850 }
1851 disable_irq(complt_irq);
1852
1853 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1854 if (res.a0) {
1855 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n", res.a0);
1856 return -ENOMEM;
1857 }
1858
1859 ret = rockchip_get_freq_info(dmcfreq);
1860 if (ret < 0) {
1861 dev_err(&pdev->dev, "cannot get frequency info\n");
1862 return ret;
1863 }
1864 dmcfreq->is_set_rate_direct = true;
1865
1866 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1867
1868 return 0;
1869 }
1870
rv1126_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)1871 static __maybe_unused int rv1126_dmc_init(struct platform_device *pdev,
1872 struct rockchip_dmcfreq *dmcfreq)
1873 {
1874 struct arm_smccc_res res;
1875 u32 size;
1876 int ret;
1877 int complt_irq;
1878 struct device_node *node;
1879
1880 res = sip_smc_dram(0, 0,
1881 ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1882 dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
1883 if (res.a0 || res.a1 < 0x100) {
1884 dev_err(&pdev->dev,
1885 "trusted firmware need to update or is invalid!\n");
1886 return -ENXIO;
1887 }
1888
1889 /*
1890 * first 4KB is used for interface parameters
1891 * after 4KB * N is dts parameters
1892 */
1893 size = sizeof(struct rk1808_ddr_dts_config_timing);
1894 res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
1895 SHARE_PAGE_TYPE_DDR);
1896 if (res.a0 != 0) {
1897 dev_err(&pdev->dev, "no ATF memory for init\n");
1898 return -ENOMEM;
1899 }
1900 ddr_psci_param = (struct share_params *)res.a1;
1901 of_get_rv1126_timings(&pdev->dev, pdev->dev.of_node,
1902 (uint32_t *)ddr_psci_param);
1903
1904 /* enable start dcf in kernel after dcf ready */
1905 node = of_parse_phandle(pdev->dev.of_node, "dcf", 0);
1906 wait_ctrl.regmap_dcf = syscon_node_to_regmap(node);
1907 if (IS_ERR(wait_ctrl.regmap_dcf))
1908 return PTR_ERR(wait_ctrl.regmap_dcf);
1909 wait_ctrl.dcf_en = 1;
1910
1911 init_waitqueue_head(&wait_ctrl.wait_wq);
1912 wait_ctrl.wait_en = 1;
1913 wait_ctrl.wait_time_out_ms = 17 * 5;
1914
1915 complt_irq = platform_get_irq_byname(pdev, "complete");
1916 if (complt_irq < 0) {
1917 dev_err(&pdev->dev, "no IRQ for complt_irq: %d\n",
1918 complt_irq);
1919 return complt_irq;
1920 }
1921 wait_ctrl.complt_irq = complt_irq;
1922
1923 ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
1924 0, dev_name(&pdev->dev), &wait_ctrl);
1925 if (ret < 0) {
1926 dev_err(&pdev->dev, "cannot request complt_irq\n");
1927 return ret;
1928 }
1929 disable_irq(complt_irq);
1930
1931 if (of_property_read_u32(pdev->dev.of_node, "update_drv_odt_cfg",
1932 &ddr_psci_param->update_drv_odt_cfg))
1933 ddr_psci_param->update_drv_odt_cfg = 0;
1934
1935 if (of_property_read_u32(pdev->dev.of_node, "update_deskew_cfg",
1936 &ddr_psci_param->update_deskew_cfg))
1937 ddr_psci_param->update_deskew_cfg = 0;
1938
1939 dmcfreq->set_rate_params = ddr_psci_param;
1940 rockchip_set_ddrclk_params(dmcfreq->set_rate_params);
1941 rockchip_set_ddrclk_dmcfreq_wait_complete(rockchip_dmcfreq_wait_complete);
1942
1943 res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
1944 ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1945 if (res.a0) {
1946 dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
1947 res.a0);
1948 return -ENOMEM;
1949 }
1950
1951 dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1952
1953 return 0;
1954 }
1955
1956 static const struct of_device_id rockchip_dmcfreq_of_match[] = {
1957 #if IS_ENABLED(CONFIG_CPU_PX30)
1958 { .compatible = "rockchip,px30-dmc", .data = px30_dmc_init },
1959 #endif
1960 #if IS_ENABLED(CONFIG_CPU_RK1808)
1961 { .compatible = "rockchip,rk1808-dmc", .data = rk1808_dmc_init },
1962 #endif
1963 #if IS_ENABLED(CONFIG_CPU_RK312X)
1964 { .compatible = "rockchip,rk3128-dmc", .data = rk3128_dmc_init },
1965 #endif
1966 #if IS_ENABLED(CONFIG_CPU_RK322X)
1967 { .compatible = "rockchip,rk3228-dmc", .data = rk3228_dmc_init },
1968 #endif
1969 #if IS_ENABLED(CONFIG_CPU_RK3288)
1970 { .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
1971 #endif
1972 #if IS_ENABLED(CONFIG_CPU_RK3308)
1973 { .compatible = "rockchip,rk3308-dmc", .data = NULL },
1974 #endif
1975 #if IS_ENABLED(CONFIG_CPU_RK3328)
1976 { .compatible = "rockchip,rk3328-dmc", .data = rk3328_dmc_init },
1977 #endif
1978 #if IS_ENABLED(CONFIG_CPU_RK3368)
1979 { .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
1980 #endif
1981 #if IS_ENABLED(CONFIG_CPU_RK3399)
1982 { .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
1983 #endif
1984 #if IS_ENABLED(CONFIG_CPU_RK3568)
1985 { .compatible = "rockchip,rk3568-dmc", .data = rk3568_dmc_init },
1986 #endif
1987 #if IS_ENABLED(CONFIG_CPU_RK3588)
1988 { .compatible = "rockchip,rk3588-dmc", .data = rk3588_dmc_init },
1989 #endif
1990 #if IS_ENABLED(CONFIG_CPU_RV1126)
1991 { .compatible = "rockchip,rv1126-dmc", .data = rv1126_dmc_init },
1992 #endif
1993 { },
1994 };
1995 MODULE_DEVICE_TABLE(of, rockchip_dmcfreq_of_match);
1996
rockchip_get_freq_map_talbe(struct device_node *np, char *porp_name, struct freq_map_table **table)1997 static int rockchip_get_freq_map_talbe(struct device_node *np, char *porp_name,
1998 struct freq_map_table **table)
1999 {
2000 struct freq_map_table *tbl;
2001 const struct property *prop;
2002 unsigned int temp_freq = 0;
2003 int count, i;
2004
2005 prop = of_find_property(np, porp_name, NULL);
2006 if (!prop)
2007 return -EINVAL;
2008
2009 if (!prop->value)
2010 return -ENODATA;
2011
2012 count = of_property_count_u32_elems(np, porp_name);
2013 if (count < 0)
2014 return -EINVAL;
2015
2016 if (count % 3)
2017 return -EINVAL;
2018
2019 tbl = kzalloc(sizeof(*tbl) * (count / 3 + 1), GFP_KERNEL);
2020 if (!tbl)
2021 return -ENOMEM;
2022
2023 for (i = 0; i < count / 3; i++) {
2024 of_property_read_u32_index(np, porp_name, 3 * i, &tbl[i].min);
2025 of_property_read_u32_index(np, porp_name, 3 * i + 1,
2026 &tbl[i].max);
2027 of_property_read_u32_index(np, porp_name, 3 * i + 2,
2028 &temp_freq);
2029 tbl[i].freq = temp_freq * 1000;
2030 }
2031
2032 tbl[i].min = 0;
2033 tbl[i].max = 0;
2034 tbl[i].freq = DMCFREQ_TABLE_END;
2035
2036 *table = tbl;
2037
2038 return 0;
2039 }
2040
rockchip_get_rl_map_talbe(struct device_node *np, char *porp_name, struct rl_map_table **table)2041 static int rockchip_get_rl_map_talbe(struct device_node *np, char *porp_name,
2042 struct rl_map_table **table)
2043 {
2044 struct rl_map_table *tbl;
2045 const struct property *prop;
2046 int count, i;
2047
2048 prop = of_find_property(np, porp_name, NULL);
2049 if (!prop)
2050 return -EINVAL;
2051
2052 if (!prop->value)
2053 return -ENODATA;
2054
2055 count = of_property_count_u32_elems(np, porp_name);
2056 if (count < 0)
2057 return -EINVAL;
2058
2059 if (count % 2)
2060 return -EINVAL;
2061
2062 tbl = kzalloc(sizeof(*tbl) * (count / 2 + 1), GFP_KERNEL);
2063 if (!tbl)
2064 return -ENOMEM;
2065
2066 for (i = 0; i < count / 2; i++) {
2067 of_property_read_u32_index(np, porp_name, 2 * i, &tbl[i].pn);
2068 of_property_read_u32_index(np, porp_name, 2 * i + 1,
2069 &tbl[i].rl);
2070 }
2071
2072 tbl[i].pn = 0;
2073 tbl[i].rl = DMCFREQ_TABLE_END;
2074
2075 *table = tbl;
2076
2077 return 0;
2078 }
2079
rockchip_get_system_status_rate(struct device_node *np, char *porp_name, struct rockchip_dmcfreq *dmcfreq)2080 static int rockchip_get_system_status_rate(struct device_node *np,
2081 char *porp_name,
2082 struct rockchip_dmcfreq *dmcfreq)
2083 {
2084 const struct property *prop;
2085 unsigned int status = 0, freq = 0;
2086 unsigned long temp_rate = 0;
2087 int count, i;
2088
2089 prop = of_find_property(np, porp_name, NULL);
2090 if (!prop)
2091 return -ENODEV;
2092
2093 if (!prop->value)
2094 return -ENODATA;
2095
2096 count = of_property_count_u32_elems(np, porp_name);
2097 if (count < 0)
2098 return -EINVAL;
2099
2100 if (count % 2)
2101 return -EINVAL;
2102
2103 for (i = 0; i < count / 2; i++) {
2104 of_property_read_u32_index(np, porp_name, 2 * i,
2105 &status);
2106 of_property_read_u32_index(np, porp_name, 2 * i + 1,
2107 &freq);
2108 switch (status) {
2109 case SYS_STATUS_NORMAL:
2110 dmcfreq->normal_rate = freq * 1000;
2111 break;
2112 case SYS_STATUS_SUSPEND:
2113 dmcfreq->suspend_rate = freq * 1000;
2114 break;
2115 case SYS_STATUS_VIDEO_1080P:
2116 dmcfreq->video_1080p_rate = freq * 1000;
2117 break;
2118 case SYS_STATUS_VIDEO_4K:
2119 dmcfreq->video_4k_rate = freq * 1000;
2120 break;
2121 case SYS_STATUS_VIDEO_4K_10B:
2122 dmcfreq->video_4k_10b_rate = freq * 1000;
2123 break;
2124 case SYS_STATUS_PERFORMANCE:
2125 dmcfreq->performance_rate = freq * 1000;
2126 break;
2127 case SYS_STATUS_HDMI:
2128 dmcfreq->hdmi_rate = freq * 1000;
2129 break;
2130 case SYS_STATUS_IDLE:
2131 dmcfreq->idle_rate = freq * 1000;
2132 break;
2133 case SYS_STATUS_REBOOT:
2134 dmcfreq->reboot_rate = freq * 1000;
2135 break;
2136 case SYS_STATUS_BOOST:
2137 dmcfreq->boost_rate = freq * 1000;
2138 break;
2139 case SYS_STATUS_ISP:
2140 case SYS_STATUS_CIF0:
2141 case SYS_STATUS_CIF1:
2142 case SYS_STATUS_DUALVIEW:
2143 temp_rate = freq * 1000;
2144 if (dmcfreq->fixed_rate < temp_rate)
2145 dmcfreq->fixed_rate = temp_rate;
2146 break;
2147 case SYS_STATUS_LOW_POWER:
2148 dmcfreq->low_power_rate = freq * 1000;
2149 break;
2150 default:
2151 break;
2152 }
2153 }
2154
2155 return 0;
2156 }
2157
rockchip_freq_level_2_rate(struct rockchip_dmcfreq *dmcfreq, unsigned int level)2158 static unsigned long rockchip_freq_level_2_rate(struct rockchip_dmcfreq *dmcfreq,
2159 unsigned int level)
2160 {
2161 unsigned long rate = 0;
2162
2163 switch (level) {
2164 case DMC_FREQ_LEVEL_LOW:
2165 rate = dmcfreq->rate_low;
2166 break;
2167 case DMC_FREQ_LEVEL_MID_LOW:
2168 rate = dmcfreq->rate_mid_low;
2169 break;
2170 case DMC_FREQ_LEVEL_MID_HIGH:
2171 rate = dmcfreq->rate_mid_high;
2172 break;
2173 case DMC_FREQ_LEVEL_HIGH:
2174 rate = dmcfreq->rate_high;
2175 break;
2176 default:
2177 break;
2178 }
2179
2180 return rate;
2181 }
2182
rockchip_get_system_status_level(struct device_node *np, char *porp_name, struct rockchip_dmcfreq *dmcfreq)2183 static int rockchip_get_system_status_level(struct device_node *np,
2184 char *porp_name,
2185 struct rockchip_dmcfreq *dmcfreq)
2186 {
2187 const struct property *prop;
2188 unsigned int status = 0, level = 0;
2189 unsigned long temp_rate = 0;
2190 int count, i;
2191
2192 prop = of_find_property(np, porp_name, NULL);
2193 if (!prop)
2194 return -ENODEV;
2195
2196 if (!prop->value)
2197 return -ENODATA;
2198
2199 count = of_property_count_u32_elems(np, porp_name);
2200 if (count < 0)
2201 return -EINVAL;
2202
2203 if (count % 2)
2204 return -EINVAL;
2205
2206 if (dmcfreq->freq_count == 1) {
2207 dmcfreq->rate_low = dmcfreq->freq_info_rate[0];
2208 dmcfreq->rate_mid_low = dmcfreq->freq_info_rate[0];
2209 dmcfreq->rate_mid_high = dmcfreq->freq_info_rate[0];
2210 dmcfreq->rate_high = dmcfreq->freq_info_rate[0];
2211 } else if (dmcfreq->freq_count == 2) {
2212 dmcfreq->rate_low = dmcfreq->freq_info_rate[0];
2213 dmcfreq->rate_mid_low = dmcfreq->freq_info_rate[0];
2214 dmcfreq->rate_mid_high = dmcfreq->freq_info_rate[1];
2215 dmcfreq->rate_high = dmcfreq->freq_info_rate[1];
2216 } else if (dmcfreq->freq_count == 3) {
2217 dmcfreq->rate_low = dmcfreq->freq_info_rate[0];
2218 dmcfreq->rate_mid_low = dmcfreq->freq_info_rate[1];
2219 dmcfreq->rate_mid_high = dmcfreq->freq_info_rate[1];
2220 dmcfreq->rate_high = dmcfreq->freq_info_rate[2];
2221 } else if (dmcfreq->freq_count == 4) {
2222 dmcfreq->rate_low = dmcfreq->freq_info_rate[0];
2223 dmcfreq->rate_mid_low = dmcfreq->freq_info_rate[1];
2224 dmcfreq->rate_mid_high = dmcfreq->freq_info_rate[2];
2225 dmcfreq->rate_high = dmcfreq->freq_info_rate[3];
2226 } else if (dmcfreq->freq_count == 5 || dmcfreq->freq_count == 6) {
2227 dmcfreq->rate_low = dmcfreq->freq_info_rate[0];
2228 dmcfreq->rate_mid_low = dmcfreq->freq_info_rate[1];
2229 dmcfreq->rate_mid_high = dmcfreq->freq_info_rate[dmcfreq->freq_count - 2];
2230 dmcfreq->rate_high = dmcfreq->freq_info_rate[dmcfreq->freq_count - 1];
2231 } else {
2232 return -EINVAL;
2233 }
2234
2235 dmcfreq->auto_min_rate = dmcfreq->rate_low;
2236
2237 for (i = 0; i < count / 2; i++) {
2238 of_property_read_u32_index(np, porp_name, 2 * i,
2239 &status);
2240 of_property_read_u32_index(np, porp_name, 2 * i + 1,
2241 &level);
2242 switch (status) {
2243 case SYS_STATUS_NORMAL:
2244 dmcfreq->normal_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2245 dev_info(dmcfreq->dev, "normal_rate = %ld\n", dmcfreq->normal_rate);
2246 break;
2247 case SYS_STATUS_SUSPEND:
2248 dmcfreq->suspend_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2249 dev_info(dmcfreq->dev, "suspend_rate = %ld\n", dmcfreq->suspend_rate);
2250 break;
2251 case SYS_STATUS_VIDEO_1080P:
2252 dmcfreq->video_1080p_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2253 dev_info(dmcfreq->dev, "video_1080p_rate = %ld\n",
2254 dmcfreq->video_1080p_rate);
2255 break;
2256 case SYS_STATUS_VIDEO_4K:
2257 dmcfreq->video_4k_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2258 dev_info(dmcfreq->dev, "video_4k_rate = %ld\n", dmcfreq->video_4k_rate);
2259 break;
2260 case SYS_STATUS_VIDEO_4K_10B:
2261 dmcfreq->video_4k_10b_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2262 dev_info(dmcfreq->dev, "video_4k_10b_rate = %ld\n",
2263 dmcfreq->video_4k_10b_rate);
2264 break;
2265 case SYS_STATUS_PERFORMANCE:
2266 dmcfreq->performance_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2267 dev_info(dmcfreq->dev, "performance_rate = %ld\n",
2268 dmcfreq->performance_rate);
2269 break;
2270 case SYS_STATUS_HDMI:
2271 dmcfreq->hdmi_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2272 dev_info(dmcfreq->dev, "hdmi_rate = %ld\n", dmcfreq->hdmi_rate);
2273 break;
2274 case SYS_STATUS_IDLE:
2275 dmcfreq->idle_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2276 dev_info(dmcfreq->dev, "idle_rate = %ld\n", dmcfreq->idle_rate);
2277 break;
2278 case SYS_STATUS_REBOOT:
2279 dmcfreq->reboot_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2280 dev_info(dmcfreq->dev, "reboot_rate = %ld\n", dmcfreq->reboot_rate);
2281 break;
2282 case SYS_STATUS_BOOST:
2283 dmcfreq->boost_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2284 dev_info(dmcfreq->dev, "boost_rate = %ld\n", dmcfreq->boost_rate);
2285 break;
2286 case SYS_STATUS_ISP:
2287 case SYS_STATUS_CIF0:
2288 case SYS_STATUS_CIF1:
2289 case SYS_STATUS_DUALVIEW:
2290 temp_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2291 if (dmcfreq->fixed_rate < temp_rate) {
2292 dmcfreq->fixed_rate = temp_rate;
2293 dev_info(dmcfreq->dev,
2294 "fixed_rate(isp|cif0|cif1|dualview) = %ld\n",
2295 dmcfreq->fixed_rate);
2296 }
2297 break;
2298 case SYS_STATUS_LOW_POWER:
2299 dmcfreq->low_power_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2300 dev_info(dmcfreq->dev, "low_power_rate = %ld\n", dmcfreq->low_power_rate);
2301 break;
2302 default:
2303 break;
2304 }
2305 }
2306
2307 return 0;
2308 }
2309
rockchip_dmcfreq_update_target(struct rockchip_dmcfreq *dmcfreq)2310 static void rockchip_dmcfreq_update_target(struct rockchip_dmcfreq *dmcfreq)
2311 {
2312 struct devfreq *devfreq = dmcfreq->info.devfreq;
2313
2314 mutex_lock(&devfreq->lock);
2315 update_devfreq(devfreq);
2316 mutex_unlock(&devfreq->lock);
2317 }
2318
rockchip_dmcfreq_system_status_notifier(struct notifier_block *nb, unsigned long status, void *ptr)2319 static int rockchip_dmcfreq_system_status_notifier(struct notifier_block *nb,
2320 unsigned long status,
2321 void *ptr)
2322 {
2323 struct rockchip_dmcfreq *dmcfreq = system_status_to_dmcfreq(nb);
2324 unsigned long target_rate = 0;
2325 unsigned int refresh = false;
2326 bool is_fixed = false;
2327
2328 if (dmcfreq->fixed_rate && (is_dualview(status) || is_isp(status))) {
2329 if (dmcfreq->is_fixed)
2330 return NOTIFY_OK;
2331 is_fixed = true;
2332 target_rate = dmcfreq->fixed_rate;
2333 goto next;
2334 }
2335
2336 if (dmcfreq->reboot_rate && (status & SYS_STATUS_REBOOT)) {
2337 if (dmcfreq->info.auto_freq_en)
2338 devfreq_monitor_stop(dmcfreq->info.devfreq);
2339 target_rate = dmcfreq->reboot_rate;
2340 goto next;
2341 }
2342
2343 if (dmcfreq->suspend_rate && (status & SYS_STATUS_SUSPEND)) {
2344 target_rate = dmcfreq->suspend_rate;
2345 refresh = true;
2346 goto next;
2347 }
2348
2349 if (dmcfreq->low_power_rate && (status & SYS_STATUS_LOW_POWER)) {
2350 target_rate = dmcfreq->low_power_rate;
2351 goto next;
2352 }
2353
2354 if (dmcfreq->performance_rate && (status & SYS_STATUS_PERFORMANCE)) {
2355 if (dmcfreq->performance_rate > target_rate)
2356 target_rate = dmcfreq->performance_rate;
2357 }
2358
2359 if (dmcfreq->hdmi_rate && (status & SYS_STATUS_HDMI)) {
2360 if (dmcfreq->hdmi_rate > target_rate)
2361 target_rate = dmcfreq->hdmi_rate;
2362 }
2363
2364 if (dmcfreq->video_4k_rate && (status & SYS_STATUS_VIDEO_4K)) {
2365 if (dmcfreq->video_4k_rate > target_rate)
2366 target_rate = dmcfreq->video_4k_rate;
2367 }
2368
2369 if (dmcfreq->video_4k_10b_rate && (status & SYS_STATUS_VIDEO_4K_10B)) {
2370 if (dmcfreq->video_4k_10b_rate > target_rate)
2371 target_rate = dmcfreq->video_4k_10b_rate;
2372 }
2373
2374 if (dmcfreq->video_1080p_rate && (status & SYS_STATUS_VIDEO_1080P)) {
2375 if (dmcfreq->video_1080p_rate > target_rate)
2376 target_rate = dmcfreq->video_1080p_rate;
2377 }
2378
2379 next:
2380
2381 dev_dbg(dmcfreq->dev, "status=0x%x\n", (unsigned int)status);
2382 dmcfreq->is_fixed = is_fixed;
2383 dmcfreq->status_rate = target_rate;
2384 if (dmcfreq->refresh != refresh) {
2385 if (dmcfreq->set_auto_self_refresh)
2386 dmcfreq->set_auto_self_refresh(refresh);
2387 dmcfreq->refresh = refresh;
2388 }
2389 rockchip_dmcfreq_update_target(dmcfreq);
2390
2391 return NOTIFY_OK;
2392 }
2393
rockchip_dmcfreq_status_show(struct device *dev, struct device_attribute *attr, char *buf)2394 static ssize_t rockchip_dmcfreq_status_show(struct device *dev,
2395 struct device_attribute *attr,
2396 char *buf)
2397 {
2398 unsigned int status = rockchip_get_system_status();
2399
2400 return sprintf(buf, "0x%x\n", status);
2401 }
2402
rockchip_dmcfreq_status_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)2403 static ssize_t rockchip_dmcfreq_status_store(struct device *dev,
2404 struct device_attribute *attr,
2405 const char *buf,
2406 size_t count)
2407 {
2408 if (!count)
2409 return -EINVAL;
2410
2411 rockchip_update_system_status(buf);
2412
2413 return count;
2414 }
2415
2416 static DEVICE_ATTR(system_status, 0644, rockchip_dmcfreq_status_show,
2417 rockchip_dmcfreq_status_store);
2418
upthreshold_show(struct device *dev, struct device_attribute *attr, char *buf)2419 static ssize_t upthreshold_show(struct device *dev,
2420 struct device_attribute *attr,
2421 char *buf)
2422 {
2423 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev->parent);
2424 struct rockchip_dmcfreq_ondemand_data *data = &dmcfreq->ondemand_data;
2425
2426 return sprintf(buf, "%d\n", data->upthreshold);
2427 }
2428
upthreshold_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)2429 static ssize_t upthreshold_store(struct device *dev,
2430 struct device_attribute *attr,
2431 const char *buf,
2432 size_t count)
2433 {
2434 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev->parent);
2435 struct rockchip_dmcfreq_ondemand_data *data = &dmcfreq->ondemand_data;
2436 unsigned int value;
2437
2438 if (kstrtouint(buf, 10, &value))
2439 return -EINVAL;
2440
2441 data->upthreshold = value;
2442
2443 return count;
2444 }
2445
2446 static DEVICE_ATTR_RW(upthreshold);
2447
downdifferential_show(struct device *dev, struct device_attribute *attr, char *buf)2448 static ssize_t downdifferential_show(struct device *dev,
2449 struct device_attribute *attr,
2450 char *buf)
2451 {
2452 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev->parent);
2453 struct rockchip_dmcfreq_ondemand_data *data = &dmcfreq->ondemand_data;
2454
2455 return sprintf(buf, "%d\n", data->downdifferential);
2456 }
2457
downdifferential_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)2458 static ssize_t downdifferential_store(struct device *dev,
2459 struct device_attribute *attr,
2460 const char *buf,
2461 size_t count)
2462 {
2463 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev->parent);
2464 struct rockchip_dmcfreq_ondemand_data *data = &dmcfreq->ondemand_data;
2465 unsigned int value;
2466
2467 if (kstrtouint(buf, 10, &value))
2468 return -EINVAL;
2469
2470 data->downdifferential = value;
2471
2472 return count;
2473 }
2474
2475 static DEVICE_ATTR_RW(downdifferential);
2476
get_nocp_req_rate(struct rockchip_dmcfreq *dmcfreq)2477 static unsigned long get_nocp_req_rate(struct rockchip_dmcfreq *dmcfreq)
2478 {
2479 unsigned long target = 0, cpu_bw = 0;
2480 int i;
2481
2482 if (!dmcfreq->cpu_bw_tbl || dmcfreq->nocp_cpu_id < 0)
2483 goto out;
2484
2485 cpu_bw = dmcfreq->nocp_bw[dmcfreq->nocp_cpu_id];
2486
2487 for (i = 0; dmcfreq->cpu_bw_tbl[i].freq != CPUFREQ_TABLE_END; i++) {
2488 if (cpu_bw >= dmcfreq->cpu_bw_tbl[i].min)
2489 target = dmcfreq->cpu_bw_tbl[i].freq;
2490 }
2491
2492 out:
2493 return target;
2494 }
2495
devfreq_dmc_ondemand_func(struct devfreq *df, unsigned long *freq)2496 static int devfreq_dmc_ondemand_func(struct devfreq *df,
2497 unsigned long *freq)
2498 {
2499 int err;
2500 struct devfreq_dev_status *stat;
2501 unsigned long long a, b;
2502 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(df->dev.parent);
2503 struct rockchip_dmcfreq_ondemand_data *data = &dmcfreq->ondemand_data;
2504 unsigned int upthreshold = data->upthreshold;
2505 unsigned int downdifferential = data->downdifferential;
2506 unsigned long target_freq = 0, nocp_req_rate = 0;
2507 u64 now;
2508
2509 if (dmcfreq->info.auto_freq_en && !dmcfreq->is_fixed) {
2510 if (dmcfreq->status_rate)
2511 target_freq = dmcfreq->status_rate;
2512 else if (dmcfreq->auto_min_rate)
2513 target_freq = dmcfreq->auto_min_rate;
2514 nocp_req_rate = get_nocp_req_rate(dmcfreq);
2515 target_freq = max3(target_freq, nocp_req_rate,
2516 dmcfreq->info.vop_req_rate);
2517 now = ktime_to_us(ktime_get());
2518 if (now < dmcfreq->touchboostpulse_endtime)
2519 target_freq = max(target_freq, dmcfreq->boost_rate);
2520 } else {
2521 if (dmcfreq->status_rate)
2522 target_freq = dmcfreq->status_rate;
2523 else if (dmcfreq->normal_rate)
2524 target_freq = dmcfreq->normal_rate;
2525 if (target_freq)
2526 *freq = target_freq;
2527 if (dmcfreq->info.auto_freq_en && !devfreq_update_stats(df))
2528 return 0;
2529 goto reset_last_status;
2530 }
2531
2532 if (!upthreshold || !downdifferential)
2533 goto reset_last_status;
2534
2535 if (upthreshold > 100 ||
2536 upthreshold < downdifferential)
2537 goto reset_last_status;
2538
2539 err = devfreq_update_stats(df);
2540 if (err)
2541 goto reset_last_status;
2542
2543 stat = &df->last_status;
2544
2545 /* Assume MAX if it is going to be divided by zero */
2546 if (stat->total_time == 0) {
2547 *freq = DEVFREQ_MAX_FREQ;
2548 return 0;
2549 }
2550
2551 /* Prevent overflow */
2552 if (stat->busy_time >= (1 << 24) || stat->total_time >= (1 << 24)) {
2553 stat->busy_time >>= 7;
2554 stat->total_time >>= 7;
2555 }
2556
2557 /* Set MAX if it's busy enough */
2558 if (stat->busy_time * 100 >
2559 stat->total_time * upthreshold) {
2560 *freq = DEVFREQ_MAX_FREQ;
2561 return 0;
2562 }
2563
2564 /* Set MAX if we do not know the initial frequency */
2565 if (stat->current_frequency == 0) {
2566 *freq = DEVFREQ_MAX_FREQ;
2567 return 0;
2568 }
2569
2570 /* Keep the current frequency */
2571 if (stat->busy_time * 100 >
2572 stat->total_time * (upthreshold - downdifferential)) {
2573 *freq = max(target_freq, stat->current_frequency);
2574 return 0;
2575 }
2576
2577 /* Set the desired frequency based on the load */
2578 a = stat->busy_time;
2579 a *= stat->current_frequency;
2580 b = div_u64(a, stat->total_time);
2581 b *= 100;
2582 b = div_u64(b, (upthreshold - downdifferential / 2));
2583 *freq = max_t(unsigned long, target_freq, b);
2584
2585 return 0;
2586
2587 reset_last_status:
2588 reset_last_status(df);
2589
2590 return 0;
2591 }
2592
devfreq_dmc_ondemand_handler(struct devfreq *devfreq, unsigned int event, void *data)2593 static int devfreq_dmc_ondemand_handler(struct devfreq *devfreq,
2594 unsigned int event, void *data)
2595 {
2596 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(devfreq->dev.parent);
2597
2598 if (!dmcfreq->info.auto_freq_en)
2599 return 0;
2600
2601 switch (event) {
2602 case DEVFREQ_GOV_START:
2603 devfreq_monitor_start(devfreq);
2604 break;
2605
2606 case DEVFREQ_GOV_STOP:
2607 devfreq_monitor_stop(devfreq);
2608 break;
2609
2610 case DEVFREQ_GOV_UPDATE_INTERVAL:
2611 devfreq_update_interval(devfreq, (unsigned int *)data);
2612 break;
2613
2614 case DEVFREQ_GOV_SUSPEND:
2615 devfreq_monitor_suspend(devfreq);
2616 break;
2617
2618 case DEVFREQ_GOV_RESUME:
2619 devfreq_monitor_resume(devfreq);
2620 break;
2621
2622 default:
2623 break;
2624 }
2625
2626 return 0;
2627 }
2628
2629 static struct devfreq_governor devfreq_dmc_ondemand = {
2630 .name = "dmc_ondemand",
2631 .get_target_freq = devfreq_dmc_ondemand_func,
2632 .event_handler = devfreq_dmc_ondemand_handler,
2633 };
2634
rockchip_dmcfreq_enable_event(struct rockchip_dmcfreq *dmcfreq)2635 static int rockchip_dmcfreq_enable_event(struct rockchip_dmcfreq *dmcfreq)
2636 {
2637 int i, ret;
2638
2639 if (!dmcfreq->info.auto_freq_en)
2640 return 0;
2641
2642 for (i = 0; i < dmcfreq->edev_count; i++) {
2643 ret = devfreq_event_enable_edev(dmcfreq->edev[i]);
2644 if (ret < 0) {
2645 dev_err(dmcfreq->dev,
2646 "failed to enable devfreq-event\n");
2647 return ret;
2648 }
2649 }
2650
2651 return 0;
2652 }
2653
rockchip_dmcfreq_disable_event(struct rockchip_dmcfreq *dmcfreq)2654 static int rockchip_dmcfreq_disable_event(struct rockchip_dmcfreq *dmcfreq)
2655 {
2656 int i, ret;
2657
2658 if (!dmcfreq->info.auto_freq_en)
2659 return 0;
2660
2661 for (i = 0; i < dmcfreq->edev_count; i++) {
2662 ret = devfreq_event_disable_edev(dmcfreq->edev[i]);
2663 if (ret < 0) {
2664 dev_err(dmcfreq->dev,
2665 "failed to disable devfreq-event\n");
2666 return ret;
2667 }
2668 }
2669
2670 return 0;
2671 }
2672
rockchip_get_edev_id(struct rockchip_dmcfreq *dmcfreq, const char *name)2673 static int rockchip_get_edev_id(struct rockchip_dmcfreq *dmcfreq,
2674 const char *name)
2675 {
2676 struct devfreq_event_dev *edev;
2677 int i;
2678
2679 for (i = 0; i < dmcfreq->edev_count; i++) {
2680 edev = dmcfreq->edev[i];
2681 if (!strcmp(edev->desc->name, name))
2682 return i;
2683 }
2684
2685 return -EINVAL;
2686 }
2687
rockchip_dmcfreq_get_event(struct rockchip_dmcfreq *dmcfreq)2688 static int rockchip_dmcfreq_get_event(struct rockchip_dmcfreq *dmcfreq)
2689 {
2690 struct device *dev = dmcfreq->dev;
2691 struct device_node *events_np, *np = dev->of_node;
2692 int i, j, count, available_count = 0;
2693
2694 count = devfreq_event_get_edev_count(dev, "devfreq-events");
2695 if (count < 0) {
2696 dev_dbg(dev, "failed to get count of devfreq-event dev\n");
2697 return 0;
2698 }
2699 for (i = 0; i < count; i++) {
2700 events_np = of_parse_phandle(np, "devfreq-events", i);
2701 if (!events_np)
2702 continue;
2703 if (of_device_is_available(events_np))
2704 available_count++;
2705 of_node_put(events_np);
2706 }
2707 if (!available_count) {
2708 dev_dbg(dev, "failed to get available devfreq-event\n");
2709 return 0;
2710 }
2711 dmcfreq->edev_count = available_count;
2712 dmcfreq->edev = devm_kzalloc(dev,
2713 sizeof(*dmcfreq->edev) * available_count,
2714 GFP_KERNEL);
2715 if (!dmcfreq->edev)
2716 return -ENOMEM;
2717
2718 for (i = 0, j = 0; i < count; i++) {
2719 events_np = of_parse_phandle(np, "devfreq-events", i);
2720 if (!events_np)
2721 continue;
2722 if (of_device_is_available(events_np)) {
2723 of_node_put(events_np);
2724 if (j >= available_count) {
2725 dev_err(dev, "invalid event conut\n");
2726 return -EINVAL;
2727 }
2728 dmcfreq->edev[j] =
2729 devfreq_event_get_edev_by_phandle(dev, "devfreq-events", i);
2730 if (IS_ERR(dmcfreq->edev[j]))
2731 return -EPROBE_DEFER;
2732 j++;
2733 } else {
2734 of_node_put(events_np);
2735 }
2736 }
2737 dmcfreq->info.auto_freq_en = true;
2738 dmcfreq->dfi_id = rockchip_get_edev_id(dmcfreq, "dfi");
2739 dmcfreq->nocp_cpu_id = rockchip_get_edev_id(dmcfreq, "nocp-cpu");
2740 dmcfreq->nocp_bw =
2741 devm_kzalloc(dev, sizeof(*dmcfreq->nocp_bw) * available_count,
2742 GFP_KERNEL);
2743 if (!dmcfreq->nocp_bw)
2744 return -ENOMEM;
2745
2746 return 0;
2747 }
2748
rockchip_dmcfreq_power_control(struct rockchip_dmcfreq *dmcfreq)2749 static int rockchip_dmcfreq_power_control(struct rockchip_dmcfreq *dmcfreq)
2750 {
2751 struct device *dev = dmcfreq->dev;
2752
2753 dmcfreq->vdd_center = devm_regulator_get_optional(dev, "center");
2754 if (IS_ERR(dmcfreq->vdd_center)) {
2755 dev_err(dev, "Cannot get the regulator \"center\"\n");
2756 return PTR_ERR(dmcfreq->vdd_center);
2757 }
2758
2759 dmcfreq->dmc_clk = devm_clk_get(dev, "dmc_clk");
2760 if (IS_ERR(dmcfreq->dmc_clk)) {
2761 dev_err(dev, "Cannot get the clk dmc_clk. If using SCMI, trusted firmware need update to V1.01 and above.\n");
2762 return PTR_ERR(dmcfreq->dmc_clk);
2763 }
2764 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
2765
2766 return 0;
2767 }
2768
rockchip_dmcfreq_dmc_init(struct platform_device *pdev, struct rockchip_dmcfreq *dmcfreq)2769 static int rockchip_dmcfreq_dmc_init(struct platform_device *pdev,
2770 struct rockchip_dmcfreq *dmcfreq)
2771 {
2772 const struct of_device_id *match;
2773 int (*init)(struct platform_device *pdev,
2774 struct rockchip_dmcfreq *data);
2775 int ret;
2776
2777 match = of_match_node(rockchip_dmcfreq_of_match, pdev->dev.of_node);
2778 if (match) {
2779 init = match->data;
2780 if (init) {
2781 ret = init(pdev, dmcfreq);
2782 if (ret)
2783 return ret;
2784 }
2785 }
2786
2787 return 0;
2788 }
2789
rockchip_dmcfreq_parse_dt(struct rockchip_dmcfreq *dmcfreq)2790 static void rockchip_dmcfreq_parse_dt(struct rockchip_dmcfreq *dmcfreq)
2791 {
2792 struct device *dev = dmcfreq->dev;
2793 struct device_node *np = dev->of_node;
2794
2795 if (!rockchip_get_system_status_rate(np, "system-status-freq", dmcfreq))
2796 dmcfreq->system_status_en = true;
2797 else if (!rockchip_get_system_status_level(np, "system-status-level", dmcfreq))
2798 dmcfreq->system_status_en = true;
2799
2800 of_property_read_u32(np, "min-cpu-freq", &dmcfreq->min_cpu_freq);
2801
2802 of_property_read_u32(np, "upthreshold",
2803 &dmcfreq->ondemand_data.upthreshold);
2804 of_property_read_u32(np, "downdifferential",
2805 &dmcfreq->ondemand_data.downdifferential);
2806 if (dmcfreq->info.auto_freq_en)
2807 of_property_read_u32(np, "auto-freq-en",
2808 &dmcfreq->info.auto_freq_en);
2809 if (!dmcfreq->auto_min_rate) {
2810 of_property_read_u32(np, "auto-min-freq",
2811 (u32 *)&dmcfreq->auto_min_rate);
2812 dmcfreq->auto_min_rate *= 1000;
2813 }
2814
2815 if (rockchip_get_freq_map_talbe(np, "cpu-bw-dmc-freq",
2816 &dmcfreq->cpu_bw_tbl))
2817 dev_dbg(dev, "failed to get cpu bandwidth to dmc rate\n");
2818 if (rockchip_get_freq_map_talbe(np, "vop-frame-bw-dmc-freq",
2819 &dmcfreq->info.vop_frame_bw_tbl))
2820 dev_dbg(dev, "failed to get vop frame bandwidth to dmc rate\n");
2821 if (rockchip_get_freq_map_talbe(np, "vop-bw-dmc-freq",
2822 &dmcfreq->info.vop_bw_tbl))
2823 dev_err(dev, "failed to get vop bandwidth to dmc rate\n");
2824 if (rockchip_get_rl_map_talbe(np, "vop-pn-msch-readlatency",
2825 &dmcfreq->info.vop_pn_rl_tbl))
2826 dev_err(dev, "failed to get vop pn to msch rl\n");
2827
2828 of_property_read_u32(np, "touchboost_duration",
2829 (u32 *)&dmcfreq->touchboostpulse_duration_val);
2830 if (dmcfreq->touchboostpulse_duration_val)
2831 dmcfreq->touchboostpulse_duration_val *= USEC_PER_MSEC;
2832 else
2833 dmcfreq->touchboostpulse_duration_val = 500 * USEC_PER_MSEC;
2834 }
2835
rockchip_dmcfreq_set_volt_only(struct rockchip_dmcfreq *dmcfreq)2836 static int rockchip_dmcfreq_set_volt_only(struct rockchip_dmcfreq *dmcfreq)
2837 {
2838 struct device *dev = dmcfreq->dev;
2839 struct dev_pm_opp *opp;
2840 unsigned long opp_volt, opp_rate = dmcfreq->rate;
2841 int ret;
2842
2843 opp = devfreq_recommended_opp(dev, &opp_rate, 0);
2844 if (IS_ERR(opp)) {
2845 dev_err(dev, "Failed to find opp for %lu Hz\n", opp_rate);
2846 return PTR_ERR(opp);
2847 }
2848 opp_volt = dev_pm_opp_get_voltage(opp);
2849 dev_pm_opp_put(opp);
2850
2851 ret = regulator_set_voltage(dmcfreq->vdd_center, opp_volt, INT_MAX);
2852 if (ret) {
2853 dev_err(dev, "Cannot set voltage %lu uV\n", opp_volt);
2854 return ret;
2855 }
2856
2857 return 0;
2858 }
2859
rockchip_dmcfreq_add_devfreq(struct rockchip_dmcfreq *dmcfreq)2860 static int rockchip_dmcfreq_add_devfreq(struct rockchip_dmcfreq *dmcfreq)
2861 {
2862 struct devfreq_dev_profile *devp = &rockchip_devfreq_dmc_profile;
2863 struct device *dev = dmcfreq->dev;
2864 struct dev_pm_opp *opp;
2865 struct devfreq *devfreq;
2866 unsigned long opp_rate = dmcfreq->rate;
2867
2868 opp = devfreq_recommended_opp(dev, &opp_rate, 0);
2869 if (IS_ERR(opp)) {
2870 dev_err(dev, "Failed to find opp for %lu Hz\n", opp_rate);
2871 return PTR_ERR(opp);
2872 }
2873 dev_pm_opp_put(opp);
2874
2875 devp->initial_freq = dmcfreq->rate;
2876 devfreq = devm_devfreq_add_device(dev, devp, "dmc_ondemand",
2877 &dmcfreq->ondemand_data);
2878 if (IS_ERR(devfreq)) {
2879 dev_err(dev, "failed to add devfreq\n");
2880 return PTR_ERR(devfreq);
2881 }
2882
2883 devm_devfreq_register_opp_notifier(dev, devfreq);
2884
2885 devfreq->last_status.current_frequency = opp_rate;
2886
2887 reset_last_status(devfreq);
2888
2889 dmcfreq->info.devfreq = devfreq;
2890
2891 return 0;
2892 }
2893
2894 static struct monitor_dev_profile dmc_mdevp = {
2895 .type = MONITOR_TPYE_DEV,
2896 .low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
2897 .high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
2898 };
2899
rockchip_dmcfreq_register_notifier(struct rockchip_dmcfreq *dmcfreq)2900 static void rockchip_dmcfreq_register_notifier(struct rockchip_dmcfreq *dmcfreq)
2901 {
2902 int ret;
2903
2904 if (vop_register_dmc())
2905 dev_err(dmcfreq->dev, "fail to register notify to vop.\n");
2906
2907 dmcfreq->status_nb.notifier_call =
2908 rockchip_dmcfreq_system_status_notifier;
2909 ret = rockchip_register_system_status_notifier(&dmcfreq->status_nb);
2910 if (ret)
2911 dev_err(dmcfreq->dev, "failed to register system_status nb\n");
2912
2913 dmc_mdevp.data = dmcfreq->info.devfreq;
2914 dmcfreq->mdev_info = rockchip_system_monitor_register(dmcfreq->dev,
2915 &dmc_mdevp);
2916 if (IS_ERR(dmcfreq->mdev_info)) {
2917 dev_dbg(dmcfreq->dev, "without without system monitor\n");
2918 dmcfreq->mdev_info = NULL;
2919 }
2920 }
2921
rockchip_dmcfreq_add_interface(struct rockchip_dmcfreq *dmcfreq)2922 static void rockchip_dmcfreq_add_interface(struct rockchip_dmcfreq *dmcfreq)
2923 {
2924 struct devfreq *devfreq = dmcfreq->info.devfreq;
2925
2926 if (sysfs_create_file(&devfreq->dev.kobj, &dev_attr_upthreshold.attr))
2927 dev_err(dmcfreq->dev,
2928 "failed to register upthreshold sysfs file\n");
2929 if (sysfs_create_file(&devfreq->dev.kobj,
2930 &dev_attr_downdifferential.attr))
2931 dev_err(dmcfreq->dev,
2932 "failed to register downdifferential sysfs file\n");
2933
2934 if (!rockchip_add_system_status_interface(&devfreq->dev))
2935 return;
2936 if (sysfs_create_file(&devfreq->dev.kobj,
2937 &dev_attr_system_status.attr))
2938 dev_err(dmcfreq->dev,
2939 "failed to register system_status sysfs file\n");
2940 }
2941
rockchip_dmcfreq_boost_work(struct work_struct *work)2942 static void rockchip_dmcfreq_boost_work(struct work_struct *work)
2943 {
2944 struct rockchip_dmcfreq *dmcfreq = boost_to_dmcfreq(work);
2945
2946 rockchip_dmcfreq_update_target(dmcfreq);
2947 }
2948
rockchip_dmcfreq_input_event(struct input_handle *handle, unsigned int type, unsigned int code, int value)2949 static void rockchip_dmcfreq_input_event(struct input_handle *handle,
2950 unsigned int type,
2951 unsigned int code,
2952 int value)
2953 {
2954 struct rockchip_dmcfreq *dmcfreq = handle->private;
2955 u64 now, endtime;
2956
2957 if (type != EV_ABS && type != EV_KEY)
2958 return;
2959
2960 now = ktime_to_us(ktime_get());
2961 endtime = now + dmcfreq->touchboostpulse_duration_val;
2962 if (endtime < (dmcfreq->touchboostpulse_endtime + 10 * USEC_PER_MSEC))
2963 return;
2964 dmcfreq->touchboostpulse_endtime = endtime;
2965
2966 schedule_work(&dmcfreq->boost_work);
2967 }
2968
rockchip_dmcfreq_input_connect(struct input_handler *handler, struct input_dev *dev, const struct input_device_id *id)2969 static int rockchip_dmcfreq_input_connect(struct input_handler *handler,
2970 struct input_dev *dev,
2971 const struct input_device_id *id)
2972 {
2973 int error;
2974 struct input_handle *handle;
2975 struct rockchip_dmcfreq *dmcfreq = input_hd_to_dmcfreq(handler);
2976
2977 handle = kzalloc(sizeof(*handle), GFP_KERNEL);
2978 if (!handle)
2979 return -ENOMEM;
2980
2981 handle->dev = dev;
2982 handle->handler = handler;
2983 handle->name = "dmcfreq";
2984 handle->private = dmcfreq;
2985
2986 error = input_register_handle(handle);
2987 if (error)
2988 goto err2;
2989
2990 error = input_open_device(handle);
2991 if (error)
2992 goto err1;
2993
2994 return 0;
2995 err1:
2996 input_unregister_handle(handle);
2997 err2:
2998 kfree(handle);
2999 return error;
3000 }
3001
rockchip_dmcfreq_input_disconnect(struct input_handle *handle)3002 static void rockchip_dmcfreq_input_disconnect(struct input_handle *handle)
3003 {
3004 input_close_device(handle);
3005 input_unregister_handle(handle);
3006 kfree(handle);
3007 }
3008
3009 static const struct input_device_id rockchip_dmcfreq_input_ids[] = {
3010 {
3011 .flags = INPUT_DEVICE_ID_MATCH_EVBIT |
3012 INPUT_DEVICE_ID_MATCH_ABSBIT,
3013 .evbit = { BIT_MASK(EV_ABS) },
3014 .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
3015 BIT_MASK(ABS_MT_POSITION_X) |
3016 BIT_MASK(ABS_MT_POSITION_Y) },
3017 },
3018 {
3019 .flags = INPUT_DEVICE_ID_MATCH_KEYBIT |
3020 INPUT_DEVICE_ID_MATCH_ABSBIT,
3021 .keybit = { [BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH) },
3022 .absbit = { [BIT_WORD(ABS_X)] =
3023 BIT_MASK(ABS_X) | BIT_MASK(ABS_Y) },
3024 },
3025 {
3026 .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
3027 .evbit = { BIT_MASK(EV_KEY) },
3028 },
3029 { },
3030 };
3031
rockchip_dmcfreq_boost_init(struct rockchip_dmcfreq *dmcfreq)3032 static void rockchip_dmcfreq_boost_init(struct rockchip_dmcfreq *dmcfreq)
3033 {
3034 if (!dmcfreq->boost_rate)
3035 return;
3036 INIT_WORK(&dmcfreq->boost_work, rockchip_dmcfreq_boost_work);
3037 dmcfreq->input_handler.event = rockchip_dmcfreq_input_event;
3038 dmcfreq->input_handler.connect = rockchip_dmcfreq_input_connect;
3039 dmcfreq->input_handler.disconnect = rockchip_dmcfreq_input_disconnect;
3040 dmcfreq->input_handler.name = "dmcfreq";
3041 dmcfreq->input_handler.id_table = rockchip_dmcfreq_input_ids;
3042 if (input_register_handler(&dmcfreq->input_handler))
3043 dev_err(dmcfreq->dev, "failed to register input handler\n");
3044 }
3045
model_static_power(struct devfreq *devfreq, unsigned long voltage)3046 static unsigned long model_static_power(struct devfreq *devfreq,
3047 unsigned long voltage)
3048 {
3049 struct device *dev = devfreq->dev.parent;
3050 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
3051
3052 int temperature;
3053 unsigned long temp;
3054 unsigned long temp_squared, temp_cubed, temp_scaling_factor;
3055 const unsigned long voltage_cubed = (voltage * voltage * voltage) >> 10;
3056
3057 if (!IS_ERR_OR_NULL(dmcfreq->ddr_tz) && dmcfreq->ddr_tz->ops->get_temp) {
3058 int ret;
3059
3060 ret =
3061 dmcfreq->ddr_tz->ops->get_temp(dmcfreq->ddr_tz,
3062 &temperature);
3063 if (ret) {
3064 dev_warn_ratelimited(dev,
3065 "failed to read temp for ddr thermal zone: %d\n",
3066 ret);
3067 temperature = FALLBACK_STATIC_TEMPERATURE;
3068 }
3069 } else {
3070 temperature = FALLBACK_STATIC_TEMPERATURE;
3071 }
3072
3073 /*
3074 * Calculate the temperature scaling factor. To be applied to the
3075 * voltage scaled power.
3076 */
3077 temp = temperature / 1000;
3078 temp_squared = temp * temp;
3079 temp_cubed = temp_squared * temp;
3080 temp_scaling_factor = (dmcfreq->ts[3] * temp_cubed)
3081 + (dmcfreq->ts[2] * temp_squared)
3082 + (dmcfreq->ts[1] * temp)
3083 + dmcfreq->ts[0];
3084
3085 return (((dmcfreq->static_coefficient * voltage_cubed) >> 20)
3086 * temp_scaling_factor) / 1000000;
3087 }
3088
3089 static struct devfreq_cooling_power ddr_cooling_power_data = {
3090 .get_static_power = model_static_power,
3091 .dyn_power_coeff = 120,
3092 };
3093
ddr_power_model_simple_init(struct rockchip_dmcfreq *dmcfreq)3094 static int ddr_power_model_simple_init(struct rockchip_dmcfreq *dmcfreq)
3095 {
3096 struct device_node *power_model_node;
3097 const char *tz_name;
3098 u32 temp;
3099
3100 power_model_node = of_get_child_by_name(dmcfreq->dev->of_node,
3101 "ddr_power_model");
3102 if (!power_model_node) {
3103 dev_err(dmcfreq->dev, "could not find power_model node\n");
3104 return -ENODEV;
3105 }
3106
3107 if (of_property_read_string(power_model_node, "thermal-zone", &tz_name)) {
3108 dev_err(dmcfreq->dev, "ts in power_model not available\n");
3109 return -EINVAL;
3110 }
3111
3112 dmcfreq->ddr_tz = thermal_zone_get_zone_by_name(tz_name);
3113 if (IS_ERR(dmcfreq->ddr_tz)) {
3114 pr_warn_ratelimited
3115 ("Error getting ddr thermal zone (%ld), not yet ready?\n",
3116 PTR_ERR(dmcfreq->ddr_tz));
3117 dmcfreq->ddr_tz = NULL;
3118
3119 return -EPROBE_DEFER;
3120 }
3121
3122 if (of_property_read_u32(power_model_node, "static-power-coefficient",
3123 &dmcfreq->static_coefficient)) {
3124 dev_err(dmcfreq->dev,
3125 "static-power-coefficient not available\n");
3126 return -EINVAL;
3127 }
3128 if (of_property_read_u32(power_model_node, "dynamic-power-coefficient",
3129 &temp)) {
3130 dev_err(dmcfreq->dev,
3131 "dynamic-power-coefficient not available\n");
3132 return -EINVAL;
3133 }
3134 ddr_cooling_power_data.dyn_power_coeff = (unsigned long)temp;
3135
3136 if (of_property_read_u32_array
3137 (power_model_node, "ts", (u32 *)dmcfreq->ts, 4)) {
3138 dev_err(dmcfreq->dev, "ts in power_model not available\n");
3139 return -EINVAL;
3140 }
3141
3142 return 0;
3143 }
3144
3145 static void
rockchip_dmcfreq_register_cooling_device(struct rockchip_dmcfreq *dmcfreq)3146 rockchip_dmcfreq_register_cooling_device(struct rockchip_dmcfreq *dmcfreq)
3147 {
3148 int ret;
3149
3150 ret = ddr_power_model_simple_init(dmcfreq);
3151 if (ret)
3152 return;
3153 dmcfreq->devfreq_cooling =
3154 of_devfreq_cooling_register_power(dmcfreq->dev->of_node,
3155 dmcfreq->info.devfreq,
3156 &ddr_cooling_power_data);
3157 if (IS_ERR(dmcfreq->devfreq_cooling)) {
3158 ret = PTR_ERR(dmcfreq->devfreq_cooling);
3159 dev_err(dmcfreq->dev,
3160 "Failed to register cooling device (%d)\n",
3161 ret);
3162 }
3163 }
3164
rockchip_dmcfreq_probe(struct platform_device *pdev)3165 static int rockchip_dmcfreq_probe(struct platform_device *pdev)
3166 {
3167 struct device *dev = &pdev->dev;
3168 struct rockchip_dmcfreq *data;
3169 int ret;
3170
3171 data = devm_kzalloc(dev, sizeof(struct rockchip_dmcfreq), GFP_KERNEL);
3172 if (!data)
3173 return -ENOMEM;
3174
3175 data->dev = dev;
3176 data->info.dev = dev;
3177 mutex_init(&data->lock);
3178 INIT_LIST_HEAD(&data->video_info_list);
3179
3180 ret = rockchip_dmcfreq_get_event(data);
3181 if (ret)
3182 return ret;
3183
3184 ret = rockchip_dmcfreq_power_control(data);
3185 if (ret)
3186 return ret;
3187
3188 ret = rockchip_init_opp_table(dev, NULL, "ddr_leakage", "center");
3189 if (ret)
3190 return ret;
3191
3192 ret = rockchip_dmcfreq_dmc_init(pdev, data);
3193 if (ret)
3194 return ret;
3195
3196 rockchip_dmcfreq_parse_dt(data);
3197 if (!data->system_status_en && !data->info.auto_freq_en) {
3198 dev_info(dev, "don't add devfreq feature\n");
3199 return rockchip_dmcfreq_set_volt_only(data);
3200 }
3201
3202 cpu_latency_qos_add_request(&pm_qos, PM_QOS_DEFAULT_VALUE);
3203 platform_set_drvdata(pdev, data);
3204
3205 ret = devfreq_add_governor(&devfreq_dmc_ondemand);
3206 if (ret)
3207 return ret;
3208 ret = rockchip_dmcfreq_enable_event(data);
3209 if (ret)
3210 return ret;
3211 ret = rockchip_dmcfreq_add_devfreq(data);
3212 if (ret) {
3213 rockchip_dmcfreq_disable_event(data);
3214 return ret;
3215 }
3216
3217 rockchip_dmcfreq_register_notifier(data);
3218 rockchip_dmcfreq_add_interface(data);
3219 rockchip_dmcfreq_boost_init(data);
3220 rockchip_dmcfreq_vop_bandwidth_init(&data->info);
3221 rockchip_dmcfreq_register_cooling_device(data);
3222
3223 rockchip_set_system_status(SYS_STATUS_NORMAL);
3224
3225 return 0;
3226 }
3227
rockchip_dmcfreq_suspend(struct device *dev)3228 static __maybe_unused int rockchip_dmcfreq_suspend(struct device *dev)
3229 {
3230 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
3231 int ret = 0;
3232
3233 if (!dmcfreq)
3234 return 0;
3235
3236 ret = rockchip_dmcfreq_disable_event(dmcfreq);
3237 if (ret)
3238 return ret;
3239
3240 ret = devfreq_suspend_device(dmcfreq->info.devfreq);
3241 if (ret < 0) {
3242 dev_err(dev, "failed to suspend the devfreq devices\n");
3243 return ret;
3244 }
3245
3246 return 0;
3247 }
3248
rockchip_dmcfreq_resume(struct device *dev)3249 static __maybe_unused int rockchip_dmcfreq_resume(struct device *dev)
3250 {
3251 struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(dev);
3252 int ret = 0;
3253
3254 if (!dmcfreq)
3255 return 0;
3256
3257 ret = rockchip_dmcfreq_enable_event(dmcfreq);
3258 if (ret)
3259 return ret;
3260
3261 ret = devfreq_resume_device(dmcfreq->info.devfreq);
3262 if (ret < 0) {
3263 dev_err(dev, "failed to resume the devfreq devices\n");
3264 return ret;
3265 }
3266 return ret;
3267 }
3268
3269 static SIMPLE_DEV_PM_OPS(rockchip_dmcfreq_pm, rockchip_dmcfreq_suspend,
3270 rockchip_dmcfreq_resume);
3271 static struct platform_driver rockchip_dmcfreq_driver = {
3272 .probe = rockchip_dmcfreq_probe,
3273 .driver = {
3274 .name = "rockchip-dmc",
3275 .pm = &rockchip_dmcfreq_pm,
3276 .of_match_table = rockchip_dmcfreq_of_match,
3277 },
3278 };
3279 module_platform_driver(rockchip_dmcfreq_driver);
3280
3281 MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
3282 MODULE_DESCRIPTION("rockchip dmcfreq driver with devfreq framework");
3283 MODULE_LICENSE("GPL v2");
3284