1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip MIPI CSI2 DPHY driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_graph.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/mfd/syscon.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
23 #include <media/v4l2-device.h>
24 #include <linux/reset.h>
25 #include "phy-rockchip-csi2-dphy-common.h"
26
27 /* GRF REG OFFSET */
28 #define GRF_VI_CON0 (0x0340)
29 #define GRF_VI_CON1 (0x0344)
30
31 /* RK3588 DPHY GRF REG OFFSET */
32 #define GRF_DPHY_CON0 (0x0)
33 #define GRF_SOC_CON2 (0x0308)
34
35 /* GRF REG BIT DEFINE */
36 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
37 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
38 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
39
40 /* RK3588 DCPHY GRF REG OFFSET */
41 #define GRF_DCPHY_CON0 (0x0)
42
43 /* PHY REG OFFSET */
44 #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
45 #define CSI2_DPHY_CTRL_PWRCTL CSI2_DPHY_CTRL_INVALID_OFFSET
46 #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
47 #define CSI2_DPHY_CLK1_LANE_EN (0x2C)
48 #define CSI2_DPHY_DUAL_CAL_EN (0x80)
49 #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
50 #define CSI2_DPHY_CLK_CALIB_EN (0x168)
51 #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
52 #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
53 #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
54 #define CSI2_DPHY_LANE1_CALIB_EN (0x268)
55 #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
56 #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
57 #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
58 #define CSI2_DPHY_LANE3_CALIB_EN (0x368)
59 #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
60 #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
61
62 #define CSI2_DCPHY_CLK_WR_THS_SETTLE (0x030)
63 #define CSI2_DCPHY_LANE0_WR_THS_SETTLE (0x130)
64 #define CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC (0x134)
65 #define CSI2_DCPHY_LANE1_WR_THS_SETTLE (0x230)
66 #define CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC (0x234)
67 #define CSI2_DCPHY_LANE2_WR_THS_SETTLE (0x330)
68 #define CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC (0x334)
69 #define CSI2_DCPHY_LANE3_WR_THS_SETTLE (0x430)
70 #define CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC (0x434)
71 #define CSI2_DCPHY_CLK_LANE_ENABLE (0x000)
72 #define CSI2_DCPHY_DATA_LANE0_ENABLE (0x100)
73 #define CSI2_DCPHY_DATA_LANE1_ENABLE (0x200)
74 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
75 #define CSI2_DCPHY_DATA_LANE3_ENABLE (0x400)
76
77 #define CSI2_DCPHY_S0C_GNR_CON1 (0x004)
78 #define CSI2_DCPHY_COMBO_S0D0_GNR_CON1 (0x104)
79 #define CSI2_DCPHY_COMBO_S0D1_GNR_CON1 (0x204)
80 #define CSI2_DCPHY_COMBO_S0D2_GNR_CON1 (0x304)
81 #define CSI2_DCPHY_S0D3_GNR_CON1 (0x304)
82
83 /* PHY REG BIT DEFINE */
84 #define CSI2_DPHY_LANE_MODE_FULL (0x4)
85 #define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
86 #define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
87 #define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
88 #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
89 #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
90 #define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
91 #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
92
93 #define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
94 #define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
95 #define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
96
97 enum csi2_dphy_index {
98 DPHY0 = 0x0,
99 DPHY1,
100 DPHY2,
101 };
102
103 enum csi2_dphy_lane {
104 CSI2_DPHY_LANE_CLOCK = 0,
105 CSI2_DPHY_LANE_CLOCK1,
106 CSI2_DPHY_LANE_DATA0,
107 CSI2_DPHY_LANE_DATA1,
108 CSI2_DPHY_LANE_DATA2,
109 CSI2_DPHY_LANE_DATA3
110 };
111
112 enum grf_reg_id {
113 GRF_DPHY_RX0_TURNDISABLE = 0,
114 GRF_DPHY_RX0_FORCERXMODE,
115 GRF_DPHY_RX0_FORCETXSTOPMODE,
116 GRF_DPHY_RX0_ENABLE,
117 GRF_DPHY_RX0_TESTCLR,
118 GRF_DPHY_RX0_TESTCLK,
119 GRF_DPHY_RX0_TESTEN,
120 GRF_DPHY_RX0_TESTDIN,
121 GRF_DPHY_RX0_TURNREQUEST,
122 GRF_DPHY_RX0_TESTDOUT,
123 GRF_DPHY_TX0_TURNDISABLE,
124 GRF_DPHY_TX0_FORCERXMODE,
125 GRF_DPHY_TX0_FORCETXSTOPMODE,
126 GRF_DPHY_TX0_TURNREQUEST,
127 GRF_DPHY_TX1RX1_TURNDISABLE,
128 GRF_DPHY_TX1RX1_FORCERXMODE,
129 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
130 GRF_DPHY_TX1RX1_ENABLE,
131 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
132 GRF_DPHY_TX1RX1_BASEDIR,
133 GRF_DPHY_TX1RX1_ENABLECLK,
134 GRF_DPHY_TX1RX1_TURNREQUEST,
135 GRF_DPHY_RX1_SRC_SEL,
136 /* rk3288 only */
137 GRF_CON_DISABLE_ISP,
138 GRF_CON_ISP_DPHY_SEL,
139 GRF_DSI_CSI_TESTBUS_SEL,
140 GRF_DVP_V18SEL,
141 /* rk1808 & rk3326 & rv1126 */
142 GRF_DPHY_CSI2PHY_FORCERXMODE,
143 GRF_DPHY_CSI2PHY_CLKLANE_EN,
144 GRF_DPHY_CSI2PHY_DATALANE_EN,
145 /* rv1126 only */
146 GRF_DPHY_CLK_INV_SEL,
147 GRF_DPHY_SEL,
148 /* rk3368 only */
149 GRF_ISP_MIPI_CSI_HOST_SEL,
150 /* below is for rk3399 only */
151 GRF_DPHY_RX0_CLK_INV_SEL,
152 GRF_DPHY_RX1_CLK_INV_SEL,
153 GRF_DPHY_TX1RX1_SRC_SEL,
154 /* below is for rk3568 only */
155 GRF_DPHY_CSI2PHY_CLKLANE1_EN,
156 GRF_DPHY_CLK1_INV_SEL,
157 GRF_DPHY_ISP_CSI2PHY_SEL,
158 GRF_DPHY_CIF_CSI2PHY_SEL,
159 GRF_DPHY_CSI2PHY_LANE_SEL,
160 GRF_DPHY_CSI2PHY1_LANE_SEL,
161 GRF_DPHY_CSI2PHY_DATALANE_EN0,
162 GRF_DPHY_CSI2PHY_DATALANE_EN1,
163 GRF_CPHY_MODE,
164 GRF_DPHY_CSIHOST2_SEL,
165 GRF_DPHY_CSIHOST3_SEL,
166 GRF_DPHY_CSIHOST4_SEL,
167 GRF_DPHY_CSIHOST5_SEL,
168 };
169
170 enum csi2dphy_reg_id {
171 CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
172 CSI2PHY_CTRL_PWRCTL,
173 CSI2PHY_CTRL_DIG_RST,
174 CSI2PHY_CLK_THS_SETTLE,
175 CSI2PHY_LANE0_THS_SETTLE,
176 CSI2PHY_LANE1_THS_SETTLE,
177 CSI2PHY_LANE2_THS_SETTLE,
178 CSI2PHY_LANE3_THS_SETTLE,
179 CSI2PHY_CLK_CALIB_ENABLE,
180 CSI2PHY_LANE0_CALIB_ENABLE,
181 CSI2PHY_LANE1_CALIB_ENABLE,
182 CSI2PHY_LANE2_CALIB_ENABLE,
183 CSI2PHY_LANE3_CALIB_ENABLE,
184 // rv1126 only
185 CSI2PHY_MIPI_LVDS_MODEL,
186 CSI2PHY_LVDS_MODE,
187 // rk3568 only
188 CSI2PHY_DUAL_CLK_EN,
189 CSI2PHY_CLK1_THS_SETTLE,
190 CSI2PHY_CLK1_CALIB_ENABLE,
191 // rk3588
192 CSI2PHY_CLK_LANE_ENABLE,
193 CSI2PHY_CLK1_LANE_ENABLE,
194 CSI2PHY_DATA_LANE0_ENABLE,
195 CSI2PHY_DATA_LANE1_ENABLE,
196 CSI2PHY_DATA_LANE2_ENABLE,
197 CSI2PHY_DATA_LANE3_ENABLE,
198 CSI2PHY_LANE0_ERR_SOT_SYNC,
199 CSI2PHY_LANE1_ERR_SOT_SYNC,
200 CSI2PHY_LANE2_ERR_SOT_SYNC,
201 CSI2PHY_LANE3_ERR_SOT_SYNC,
202 CSI2PHY_S0C_GNR_CON1,
203 CSI2PHY_COMBO_S0D0_GNR_CON1,
204 CSI2PHY_COMBO_S0D1_GNR_CON1,
205 CSI2PHY_COMBO_S0D2_GNR_CON1,
206 CSI2PHY_S0D3_GNR_CON1,
207 };
208
209 #define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16))
210
211 #define GRF_REG(_offset, _width, _shift) \
212 { \
213 .offset = (_offset), .mask = BIT(_width) - 1, .shift = (_shift), \
214 }
215
216 #define CSI2PHY_REG(_offset) \
217 { \
218 .offset = (_offset), \
219 }
220
221 struct hsfreq_range {
222 u32 range_h;
223 u16 cfg_bit;
224 };
225
write_sys_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)226 static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)
227 {
228 const struct grf_reg *reg = &hw->grf_regs[index];
229 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
230
231 if (reg->shift) {
232 regmap_write(hw->regmap_sys_grf, reg->offset, val);
233 }
234 }
235
write_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)236 static inline void write_grf_reg(struct csi2_dphy_hw *hw, int index, u8 value)
237 {
238 const struct grf_reg *reg = &hw->grf_regs[index];
239 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
240
241 if (reg->shift) {
242 regmap_write(hw->regmap_grf, reg->offset, val);
243 }
244 }
245
read_grf_reg(struct csi2_dphy_hw *hw, int index)246 static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
247 {
248 const struct grf_reg *reg = &hw->grf_regs[index];
249 unsigned int val = 0;
250
251 if (reg->shift) {
252 regmap_read(hw->regmap_grf, reg->offset, &val);
253 val = (val >> reg->shift) & reg->mask;
254 }
255
256 return val;
257 }
258
write_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 value)259 static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 value)
260 {
261 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
262
263 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) || (index == CSI2PHY_CLK_LANE_ENABLE) ||
264 (index != CSI2PHY_REG_CTRL_LANE_ENABLE && reg->offset != 0x0)) {
265 writel(value, hw->hw_base_addr + reg->offset);
266 }
267 }
268
write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw, int index, u32 value, u32 mask)269 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw, int index, u32 value, u32 mask)
270 {
271 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
272 u32 read_val = 0;
273
274 read_val = readl(hw->hw_base_addr + reg->offset);
275 read_val &= ~mask;
276 read_val |= value;
277 writel(read_val, hw->hw_base_addr + reg->offset);
278 }
279
read_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 *value)280 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw, int index, u32 *value)
281 {
282 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
283
284 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) || (index == CSI2PHY_CLK_LANE_ENABLE) ||
285 (index != CSI2PHY_REG_CTRL_LANE_ENABLE && reg->offset != 0x0)) {
286 *value = readl(hw->hw_base_addr + reg->offset);
287 }
288 }
289
csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane)290 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane)
291 {
292 unsigned int val = 0;
293 unsigned int offset;
294
295 switch (lane) {
296 case CSI2_DPHY_LANE_CLOCK:
297 offset = CSI2PHY_CLK_THS_SETTLE;
298 break;
299 case CSI2_DPHY_LANE_CLOCK1:
300 offset = CSI2PHY_CLK1_THS_SETTLE;
301 break;
302 case CSI2_DPHY_LANE_DATA0:
303 offset = CSI2PHY_LANE0_THS_SETTLE;
304 break;
305 case CSI2_DPHY_LANE_DATA1:
306 offset = CSI2PHY_LANE1_THS_SETTLE;
307 break;
308 case CSI2_DPHY_LANE_DATA2:
309 offset = CSI2PHY_LANE2_THS_SETTLE;
310 break;
311 case CSI2_DPHY_LANE_DATA3:
312 offset = CSI2PHY_LANE3_THS_SETTLE;
313 break;
314 default:
315 return;
316 }
317
318 read_csi2_dphy_reg(hw, offset, &val);
319 val = (val & ~0x7f) | hsfreq;
320 write_csi2_dphy_reg(hw, offset, val);
321 }
322
323 static const struct grf_reg rk3568_grf_dphy_regs[] = {
324 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
325 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
326 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
327 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
328 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
329 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
330 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
331 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
332 [GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
333 [GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
334 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
335 };
336
337 static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
338 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
339 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
340 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
341 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
342 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
343 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
344 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
345 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
346 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
347 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
348 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
349 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
350 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
351 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
352 };
353
354 static const struct grf_reg rk3588_grf_dphy_regs[] = {
355 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
356 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
357 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
358 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
359 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
360 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
361 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
362 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
363 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
364 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
365 [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
366 [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
367 [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
368 [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
369 };
370
371 static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
372 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
373 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
374 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
375 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
376 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
377 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
378 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
379 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
380 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
381 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
382 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
383 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
384 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
385 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
386 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
387 };
388
389 static const struct grf_reg rk3588_grf_dcphy_regs[] = {
390 [GRF_CPHY_MODE] = GRF_REG(GRF_DCPHY_CON0, 9, 0),
391 };
392
393 static const struct csi2dphy_reg rk3588_csi2dcphy_regs[] = {
394 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_WR_THS_SETTLE),
395 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_THS_SETTLE),
396 [CSI2PHY_LANE0_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC),
397 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_THS_SETTLE),
398 [CSI2PHY_LANE1_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC),
399 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_THS_SETTLE),
400 [CSI2PHY_LANE2_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC),
401 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_THS_SETTLE),
402 [CSI2PHY_LANE3_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC),
403 [CSI2PHY_CLK_LANE_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_LANE_ENABLE),
404 [CSI2PHY_DATA_LANE0_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE0_ENABLE),
405 [CSI2PHY_DATA_LANE1_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE1_ENABLE),
406 [CSI2PHY_DATA_LANE2_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE2_ENABLE),
407 [CSI2PHY_DATA_LANE3_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE3_ENABLE),
408 [CSI2PHY_S0C_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0C_GNR_CON1),
409 [CSI2PHY_COMBO_S0D0_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_GNR_CON1),
410 [CSI2PHY_COMBO_S0D1_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_GNR_CON1),
411 [CSI2PHY_COMBO_S0D2_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_GNR_CON1),
412 [CSI2PHY_S0D3_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0D3_GNR_CON1),
413 };
414
415 /* These tables must be sorted by .range_h ascending. */
416 static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
417 {109, 0x02}, {149, 0x03}, {199, 0x06}, {249, 0x06}, {299, 0x06}, {399, 0x08}, {499, 0x0b},
418 {599, 0x0e}, {699, 0x10}, {799, 0x12}, {999, 0x16}, {1199, 0x1e}, {1399, 0x23}, {1599, 0x2d},
419 {1799, 0x32}, {1999, 0x37}, {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}};
420
421 /* These tables must be sorted by .range_h ascending. */
422 static const struct hsfreq_range rk3588_csi2_dcphy_d_hw_hsfreq_ranges[] = {
423 {80, 0x105}, {100, 0x106}, {120, 0x107}, {140, 0x108}, {160, 0x109}, {180, 0x10a}, {200, 0x10b},
424 {220, 0x10c}, {240, 0x10d}, {270, 0x10e}, {290, 0x10f}, {310, 0x110}, {330, 0x111}, {350, 0x112},
425 {370, 0x113}, {390, 0x114}, {410, 0x115}, {430, 0x116}, {450, 0x117}, {470, 0x118}, {490, 0x119},
426 {510, 0x11a}, {540, 0x11b}, {560, 0x11c}, {580, 0x11d}, {600, 0x11e}, {620, 0x11f}, {640, 0x120},
427 {660, 0x121}, {680, 0x122}, {700, 0x123}, {720, 0x124}, {740, 0x125}, {760, 0x126}, {790, 0x127},
428 {810, 0x128}, {830, 0x129}, {850, 0x12a}, {870, 0x12b}, {890, 0x12c}, {910, 0x12d}, {930, 0x12e},
429 {950, 0x12f}, {970, 0x130}, {990, 0x131}, {1010, 0x132}, {1030, 0x133}, {1060, 0x134}, {1080, 0x135},
430 {1100, 0x136}, {1120, 0x137}, {1140, 0x138}, {1160, 0x139}, {1180, 0x13a}, {1200, 0x13b}, {1220, 0x13c},
431 {1240, 0x13d}, {1260, 0x13e}, {1280, 0x13f}, {1310, 0x140}, {1330, 0x141}, {1350, 0x142}, {1370, 0x143},
432 {1390, 0x144}, {1410, 0x145}, {1430, 0x146}, {1450, 0x147}, {1470, 0x148}, {1490, 0x149}, {1580, 0x007},
433 {1740, 0x008}, {1910, 0x009}, {2070, 0x00a}, {2240, 0x00b}, {2410, 0x00c}, {2570, 0x00d}, {2740, 0x00e},
434 {2910, 0x00f}, {3070, 0x010}, {3240, 0x011}, {3410, 0x012}, {3570, 0x013}, {3740, 0x014}, {3890, 0x015},
435 {4070, 0x016}, {4240, 0x017}, {4400, 0x018}, {4500, 0x019},
436 };
437
438 /* These tables must be sorted by .range_h ascending. */
439 static const struct hsfreq_range rk3588_csi2_dcphy_c_hw_hsfreq_ranges[] = {
440 {500, 0x102},
441 {990, 0x002},
442 {2500, 0x001},
443 };
444
get_remote_sensor(struct v4l2_subdev *sd)445 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
446 {
447 struct media_pad *local, *remote;
448 struct media_entity *sensor_me;
449
450 local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
451 remote = media_entity_remote_pad(local);
452 if (!remote) {
453 v4l2_warn(sd, "No link between dphy and sensor\n");
454 return NULL;
455 }
456
457 sensor_me = media_entity_remote_pad(local)->entity;
458 return media_entity_to_v4l2_subdev(sensor_me);
459 }
460
sd_to_sensor(struct csi2_dphy *dphy, struct v4l2_subdev *sd)461 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy, struct v4l2_subdev *sd)
462 {
463 int i;
464
465 for (i = 0; i < dphy->num_sensors; ++i) {
466 if (dphy->sensors[i].sd == sd) {
467 return &dphy->sensors[i];
468 }
469 }
470
471 return NULL;
472 }
473
csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)474 static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
475 {
476 if (hw->rsts_bulk) {
477 reset_control_assert(hw->rsts_bulk);
478 }
479
480 udelay(0X05);
481
482 if (hw->rsts_bulk) {
483 reset_control_deassert(hw->rsts_bulk);
484 }
485 }
486
csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, struct csi2_sensor *sensor)487 static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy, struct csi2_sensor *sensor)
488 {
489 struct csi2_dphy_hw *hw = dphy->dphy_hw;
490 struct v4l2_subdev *sd = &dphy->sd;
491 bool is_cif = false;
492 char *model;
493 u32 val;
494
495 model = sd->v4l2_dev->mdev->model;
496 if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) {
497 is_cif = true;
498 } else {
499 is_cif = false;
500 }
501
502 if (hw->lane_mode == LANE_MODE_FULL) {
503 val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
504 if (dphy->phy_index < 0X03) {
505 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));
506 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
507 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
508 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
509 } else {
510 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
511 }
512 } else {
513 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0));
514 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
515 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
516 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
517 } else {
518 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
519 }
520 }
521 } else {
522 val = GRF_CSI2PHY_LANE_SEL_SPLIT;
523
524 switch (dphy->phy_index) {
525 case 1:
526 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0));
527 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
528 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
529 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
530 if (is_cif) {
531 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_0_1);
532 } else {
533 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_0_1);
534 }
535 } else {
536 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
537 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
538 }
539 break;
540 case 0X02:
541 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0));
542 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
543 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
544 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
545 if (is_cif) {
546 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_2_3);
547 } else {
548 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL, GRF_CSI2PHY_SEL_SPLIT_2_3);
549 }
550 } else {
551 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
552 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
553 }
554 break;
555 case 0X04:
556 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
557 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
558 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0, GENMASK(sensor->lanes - 1, 0));
559 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
560 break;
561 case 0X05:
562 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
563 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
564 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1, GENMASK(sensor->lanes - 1, 0));
565 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
566 break;
567 default:
568 break;
569 };
570 }
571 }
572
csi2_dphy_hw_stream_on(struct csi2_dphy *dphy, struct v4l2_subdev *sd)573 static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy, struct v4l2_subdev *sd)
574 {
575 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
576 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
577 struct csi2_dphy_hw *hw = dphy->dphy_hw;
578 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
579 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
580 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
581 int i, hsfreq = 0;
582 u32 val = 0, pre_val;
583
584 mutex_lock(&hw->mutex);
585
586 /* set data lane num and enable clock lane */
587 /*
588 * for rk356x: dphy0 is used just for full mode,
589 * dphy1 is used just for split mode,uses lane0_1,
590 * dphy2 is used just for split mode,uses lane2_3
591 */
592 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
593 if (hw->lane_mode == LANE_MODE_FULL) {
594 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
595 (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
596 } else {
597 if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT))) {
598 val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
599 }
600
601 if (dphy->phy_index % 0X03 == DPHY1) {
602 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
603 }
604
605 if (dphy->phy_index % 0x03 == DPHY2) {
606 val |= (GENMASK(sensor->lanes - 1, 0) << CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
607 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(0x06));
608 }
609 }
610 val |= pre_val;
611 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
612
613 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
614 /* Reset dphy digital part */
615 if (hw->lane_mode == LANE_MODE_FULL) {
616 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
617 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
618 } else {
619 read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
620 if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
621 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
622 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
623 }
624 }
625 csi2_dphy_config_dual_mode(dphy, sensor);
626 }
627
628 /* not into receive mode/wait stopstate */
629 write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
630
631 /* enable calibration */
632 if (dphy->data_rate_mbps > 0x5dc) {
633 if (hw->lane_mode == LANE_MODE_FULL) {
634 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
635 if (sensor->lanes > 0x00) {
636 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
637 }
638 if (sensor->lanes > 0x01) {
639 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
640 }
641 if (sensor->lanes > 0x02) {
642 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
643 }
644 if (sensor->lanes > 0x03) {
645 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
646 }
647 } else {
648 if (dphy->phy_index % 0x03 == DPHY1) {
649 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
650 if (sensor->lanes > 0x00) {
651 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
652 }
653 if (sensor->lanes > 0x01) {
654 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
655 }
656 }
657
658 if (dphy->phy_index % 0x03 == DPHY2) {
659 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
660 if (sensor->lanes > 0x00) {
661 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
662 }
663 if (sensor->lanes > 0x01) {
664 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
665 }
666 }
667 }
668 }
669
670 /* set clock lane and data lane */
671 for (i = 0; i < num_hsfreq_ranges; i++) {
672 if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
673 hsfreq = hsfreq_ranges[i].cfg_bit;
674 break;
675 }
676 }
677
678 if (i == num_hsfreq_ranges) {
679 i = num_hsfreq_ranges - 1;
680 dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps", dphy->data_rate_mbps,
681 hsfreq_ranges[i].range_h + 1);
682 hsfreq = hsfreq_ranges[i].cfg_bit;
683 }
684
685 if (hw->lane_mode == LANE_MODE_FULL) {
686 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
687 if (sensor->lanes > 0x00) {
688 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
689 }
690 if (sensor->lanes > 0x01) {
691 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
692 }
693 if (sensor->lanes > 0x02) {
694 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
695 }
696 if (sensor->lanes > 0x03) {
697 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
698 }
699 } else {
700 if (dphy->phy_index % 0x03 == DPHY1) {
701 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
702 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
703 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
704 }
705
706 if (dphy->phy_index % 0x03 == DPHY2) {
707 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
708 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
709 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
710 }
711 }
712
713 atomic_inc(&hw->stream_cnt);
714
715 mutex_unlock(&hw->mutex);
716
717 return 0;
718 }
719
csi2_dphy_hw_stream_off(struct csi2_dphy *dphy, struct v4l2_subdev *sd)720 static int csi2_dphy_hw_stream_off(struct csi2_dphy *dphy, struct v4l2_subdev *sd)
721 {
722 struct csi2_dphy_hw *hw = dphy->dphy_hw;
723
724 if (atomic_dec_return(&hw->stream_cnt)) {
725 return 0;
726 }
727
728 mutex_lock(&hw->mutex);
729
730 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
731 csi2_dphy_hw_do_reset(hw);
732 usleep_range(0x1F4, 0x3E8);
733
734 mutex_unlock(&hw->mutex);
735
736 return 0;
737 }
738
csi_dcphy_wait_lane_prepare(struct csi2_dphy_hw *hw, int index)739 static int csi_dcphy_wait_lane_prepare(struct csi2_dphy_hw *hw, int index)
740 {
741 int count = 0;
742 u32 val = 0;
743
744 read_csi2_dphy_reg(hw, index, &val);
745 while (!(val & BIT(1))) {
746 usleep_range(0x0A, 0x14);
747 read_csi2_dphy_reg(hw, index, &val);
748 count++;
749 if (count > 0x7D0) {
750 return -EINVAL;
751 }
752 }
753 return 0;
754 }
755
csi2_dcphy_hw_stream_on(struct csi2_dphy *dphy, struct v4l2_subdev *sd)756 static int csi2_dcphy_hw_stream_on(struct csi2_dphy *dphy, struct v4l2_subdev *sd)
757 {
758 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
759 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
760 struct csi2_dphy_hw *hw = dphy->dphy_hw;
761 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
762 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
763 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
764 int i, hsfreq = 0;
765 u32 sot_sync = 0;
766
767 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
768 hsfreq_ranges = drv_data->hsfreq_ranges;
769 num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
770 sot_sync = 0x03;
771 } else if (sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
772 hsfreq_ranges = drv_data->hsfreq_ranges_cphy;
773 num_hsfreq_ranges = drv_data->num_hsfreq_ranges_cphy;
774 sot_sync = 0x32;
775 }
776
777 mutex_lock(&hw->mutex);
778 if (sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
779 write_grf_reg(hw, GRF_CPHY_MODE, 0x9);
780 }
781
782 if (hw->rsts_bulk) {
783 reset_control_assert(hw->rsts_bulk);
784 }
785
786 /* clk settle fix to 0x301 */
787 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
788 write_csi2_dphy_reg(hw, CSI2PHY_CLK_THS_SETTLE, 0x301);
789 write_csi2_dphy_reg(hw, CSI2PHY_S0C_GNR_CON1, 0x1450);
790 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D0_GNR_CON1, 0x1450);
791 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D1_GNR_CON1, 0x1450);
792 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D2_GNR_CON1, 0x1450);
793 write_csi2_dphy_reg(hw, CSI2PHY_S0D3_GNR_CON1, 0x1450);
794 }
795 /* set data lane */
796 for (i = 0; i < num_hsfreq_ranges; i++) {
797 if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
798 hsfreq = hsfreq_ranges[i].cfg_bit;
799 break;
800 }
801 }
802
803 if (i == num_hsfreq_ranges) {
804 i = num_hsfreq_ranges - 1;
805 dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps", dphy->data_rate_mbps,
806 hsfreq_ranges[i].range_h + 1);
807 hsfreq = hsfreq_ranges[i].cfg_bit;
808 }
809 if (sensor->lanes > 0x00) {
810 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_THS_SETTLE, hsfreq, 0x1ff);
811 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_ERR_SOT_SYNC, sot_sync, 0xff);
812 }
813 if (sensor->lanes > 0x01) {
814 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_THS_SETTLE, hsfreq, 0x1ff);
815 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_ERR_SOT_SYNC, sot_sync, 0xff);
816 }
817 if (sensor->lanes > 0x02) {
818 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_THS_SETTLE, hsfreq, 0x1ff);
819 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_ERR_SOT_SYNC, sot_sync, 0xff);
820 }
821 if (sensor->lanes > 0x03) {
822 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_THS_SETTLE, hsfreq, 0x1ff);
823 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_ERR_SOT_SYNC, sot_sync, 0xff);
824 }
825
826 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
827 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, BIT(0));
828 }
829
830 if (sensor->lanes > 0x00) {
831 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, BIT(0));
832 }
833 if (sensor->lanes > 0x01) {
834 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, BIT(0));
835 }
836 if (sensor->lanes > 0x02) {
837 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, BIT(0));
838 }
839 if (sensor->lanes > 0x03) {
840 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, BIT(0));
841 }
842
843 /* wait for clk lane ready */
844 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
845 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_CLK_LANE_ENABLE)) {
846 goto out_streamon;
847 }
848 }
849
850 /* wait for data lane ready */
851 if (sensor->lanes > 0) {
852 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE0_ENABLE)) {
853 goto out_streamon;
854 }
855 }
856 if (sensor->lanes > 1) {
857 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE1_ENABLE)) {
858 goto out_streamon;
859 }
860 }
861 if (sensor->lanes > 0x02) {
862 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE2_ENABLE)) {
863 goto out_streamon;
864 }
865 }
866 if (sensor->lanes > 0x03) {
867 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE3_ENABLE)) {
868 goto out_streamon;
869 }
870 }
871
872 if (hw->rsts_bulk) {
873 reset_control_deassert(hw->rsts_bulk);
874 }
875 atomic_inc(&hw->stream_cnt);
876
877 mutex_unlock(&hw->mutex);
878
879 return 0;
880 out_streamon:
881 if (hw->rsts_bulk) {
882 reset_control_deassert(hw->rsts_bulk);
883 }
884 mutex_unlock(&hw->mutex);
885 dev_err(dphy->dev, "stream on error\n");
886 return -EINVAL;
887 }
888
csi2_dcphy_hw_stream_off(struct csi2_dphy *dphy, struct v4l2_subdev *sd)889 static int csi2_dcphy_hw_stream_off(struct csi2_dphy *dphy, struct v4l2_subdev *sd)
890 {
891 struct csi2_dphy_hw *hw = dphy->dphy_hw;
892 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
893 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
894
895 if (atomic_dec_return(&hw->stream_cnt)) {
896 return 0;
897 }
898
899 mutex_lock(&hw->mutex);
900 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
901 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, 0);
902 }
903 if (sensor->lanes > 0x00) {
904 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, 0);
905 }
906 if (sensor->lanes > 0x01) {
907 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, 0);
908 }
909 if (sensor->lanes > 0x02) {
910 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, 0);
911 }
912 if (sensor->lanes > 0x03) {
913 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, 0);
914 }
915
916 usleep_range(0x1F4, 0x3E8);
917
918 mutex_unlock(&hw->mutex);
919
920 return 0;
921 }
922
rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)923 static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
924 {
925 hw->grf_regs = rk3568_grf_dphy_regs;
926 }
927
rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)928 static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
929 {
930 hw->grf_regs = rk3588_grf_dphy_regs;
931 }
932
rk3588_csi2_dcphy_hw_individual_init(struct csi2_dphy_hw *hw)933 static void rk3588_csi2_dcphy_hw_individual_init(struct csi2_dphy_hw *hw)
934 {
935 hw->grf_regs = rk3588_grf_dcphy_regs;
936 }
937
938 static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
939 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
940 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
941 .csi2dphy_regs = rk3568_csi2dphy_regs,
942 .grf_regs = rk3568_grf_dphy_regs,
943 .individual_init = rk3568_csi2_dphy_hw_individual_init,
944 .chip_id = CHIP_ID_RK3568,
945 .stream_on = csi2_dphy_hw_stream_on,
946 .stream_off = csi2_dphy_hw_stream_off,
947 };
948
949 static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
950 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
951 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
952 .csi2dphy_regs = rk3588_csi2dphy_regs,
953 .grf_regs = rk3588_grf_dphy_regs,
954 .individual_init = rk3588_csi2_dphy_hw_individual_init,
955 .chip_id = CHIP_ID_RK3588,
956 .stream_on = csi2_dphy_hw_stream_on,
957 .stream_off = csi2_dphy_hw_stream_off,
958 };
959
960 static const struct dphy_hw_drv_data rk3588_csi2_dcphy_hw_drv_data = {
961 .hsfreq_ranges = rk3588_csi2_dcphy_d_hw_hsfreq_ranges,
962 .num_hsfreq_ranges = ARRAY_SIZE(rk3588_csi2_dcphy_d_hw_hsfreq_ranges),
963 .hsfreq_ranges_cphy = rk3588_csi2_dcphy_c_hw_hsfreq_ranges,
964 .num_hsfreq_ranges_cphy = ARRAY_SIZE(rk3588_csi2_dcphy_c_hw_hsfreq_ranges),
965 .csi2dphy_regs = rk3588_csi2dcphy_regs,
966 .grf_regs = rk3588_grf_dcphy_regs,
967 .individual_init = rk3588_csi2_dcphy_hw_individual_init,
968 .chip_id = CHIP_ID_RK3588_DCPHY,
969 .stream_on = csi2_dcphy_hw_stream_on,
970 .stream_off = csi2_dcphy_hw_stream_off,
971 };
972
973 static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {{
974 .compatible = "rockchip,rk3568-csi2-dphy-hw",
975 .data = &rk3568_csi2_dphy_hw_drv_data,
976 }, {
977 .compatible = "rockchip,rk3588-csi2-dphy-hw",
978 .data = &rk3588_csi2_dphy_hw_drv_data,
979 }, {
980 .compatible = "rockchip,rk3588-csi2-dcphy-hw",
981 .data = &rk3588_csi2_dcphy_hw_drv_data,
982 }, {
983 }};
984 MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id);
985
rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)986 static int rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)
987 {
988 struct device *dev = &pdev->dev;
989 struct csi2_dphy_hw *dphy_hw;
990 struct regmap *grf;
991 struct resource *res;
992 const struct of_device_id *of_id;
993 const struct dphy_hw_drv_data *drv_data;
994
995 dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
996 if (!dphy_hw) {
997 return -ENOMEM;
998 }
999 dphy_hw->dev = dev;
1000
1001 of_id = of_match_device(rockchip_csi2_dphy_hw_match_id, dev);
1002 if (!of_id) {
1003 return -EINVAL;
1004 }
1005
1006 drv_data = of_id->data;
1007
1008 grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
1009 if (IS_ERR(grf)) {
1010 dev_err(dev, "Can't find GRF syscon\n");
1011 return -ENODEV;
1012 }
1013 dphy_hw->regmap_grf = grf;
1014
1015 if (drv_data->chip_id == CHIP_ID_RK3588) {
1016 grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,sys_grf");
1017 if (IS_ERR(grf)) {
1018 dev_err(dev, "Can't find SYS GRF syscon\n");
1019 return -ENODEV;
1020 }
1021 dphy_hw->regmap_sys_grf = grf;
1022 }
1023
1024 dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
1025 if (dphy_hw->num_clks < 0) {
1026 dev_err(dev, "failed to get csi2 clks\n");
1027 }
1028
1029 dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
1030 if (IS_ERR(dphy_hw->rsts_bulk)) {
1031 dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
1032 }
1033
1034 dphy_hw->dphy_dev_num = 0;
1035 dphy_hw->drv_data = drv_data;
1036 dphy_hw->lane_mode = LANE_MODE_UNDEF;
1037 dphy_hw->grf_regs = drv_data->grf_regs;
1038 dphy_hw->txrx_regs = drv_data->txrx_regs;
1039 dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
1040
1041 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1042 dphy_hw->hw_base_addr = devm_ioremap_resource(dev, res);
1043 if (IS_ERR(dphy_hw->hw_base_addr)) {
1044 resource_size_t offset = res->start;
1045 resource_size_t size = resource_size(res);
1046
1047 dphy_hw->hw_base_addr = devm_ioremap(dev, offset, size);
1048 if (IS_ERR(dphy_hw->hw_base_addr)) {
1049 dev_err(dev, "Can't find csi2 dphy hw addr!\n");
1050 return -ENODEV;
1051 }
1052 }
1053 dphy_hw->stream_on = drv_data->stream_on;
1054 dphy_hw->stream_off = drv_data->stream_off;
1055
1056 atomic_set(&dphy_hw->stream_cnt, 0);
1057
1058 mutex_init(&dphy_hw->mutex);
1059
1060 platform_set_drvdata(pdev, dphy_hw);
1061
1062 pm_runtime_enable(&pdev->dev);
1063
1064 dev_info(dev, "csi2 dphy hw probe successfully!\n");
1065
1066 return 0;
1067 }
1068
rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)1069 static int rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)
1070 {
1071 struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
1072
1073 pm_runtime_disable(&pdev->dev);
1074 mutex_destroy(&hw->mutex);
1075
1076 return 0;
1077 }
1078
1079 static struct platform_driver rockchip_csi2_dphy_hw_driver = {
1080 .probe = rockchip_csi2_dphy_hw_probe,
1081 .remove = rockchip_csi2_dphy_hw_remove,
1082 .driver =
1083 {
1084 .name = "rockchip-csi2-dphy-hw",
1085 .of_match_table = rockchip_csi2_dphy_hw_match_id,
1086 },
1087 };
1088 module_platform_driver(rockchip_csi2_dphy_hw_driver);
1089
1090 MODULE_AUTHOR("Rockchip Camera/ISP team");
1091 MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");
1092 MODULE_LICENSE("GPL v2");
1093