Lines Matching refs:shift
527 * @shift: shift to the divider bit field
565 u8 shift;
600 void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
603 unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
612 * @shift: number of bits to shift the bitfield
617 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, lock) \
618 clk_register_divider_table((dev), (name), (parent_name), (flags), (reg), (shift), (width), (clk_divider_flags), \
627 * @shift: number of bits to shift the bitfield
632 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, lock) \
633 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (shift), (width), \
643 * @shift: number of bits to shift the bitfield
648 #define clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, reg, shift, width, clk_divider_flags, lock) \
649 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (reg), (shift), (width), \
659 * @shift: number of bits to shift the bitfield
664 #define clk_hw_register_divider_parent_data(dev, name, parent_data, flags, reg, shift, width, clk_divider_flags, lock) \
665 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (reg), (shift), (width), \
675 * @shift: number of bits to shift the bitfield
681 #define clk_hw_register_divider_table(dev, name, parent_name, flags, reg, shift, width, clk_divider_flags, table, \
683 __clk_hw_register_divider((dev), NULL, (name), (parent_name), NULL, NULL, (flags), (reg), (shift), (width), \
693 * @shift: number of bits to shift the bitfield
699 #define clk_hw_register_divider_table_parent_hw(dev, name, parent_hw, flags, reg, shift, width, clk_divider_flags, \
701 __clk_hw_register_divider((dev), NULL, (name), NULL, (parent_hw), NULL, (flags), (reg), (shift), (width), \
711 * @shift: number of bits to shift the bitfield
717 #define clk_hw_register_divider_table_parent_data(dev, name, parent_data, flags, reg, shift, width, clk_divider_flags, \
719 __clk_hw_register_divider((dev), NULL, (name), NULL, NULL, (parent_data), (flags), (reg), (shift), (width), \
731 * @shift: shift to multiplexer bit field
759 u8 shift;
779 u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, spinlock_t *lock);
781 u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
784 #define clk_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
785 clk_register_mux_table((dev), (name), (parent_names), (num_parents), (flags), (reg), (shift), BIT((width)) - 1, \
787 #define clk_hw_register_mux_table(dev, name, parent_names, num_parents, flags, reg, shift, mask, clk_mux_flags, table, \
789 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NULL, NULL, (flags), (reg), (shift), \
791 #define clk_hw_register_mux(dev, name, parent_names, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
792 __clk_hw_register_mux((dev), NULL, (name), (num_parents), (parent_names), NULL, NULL, (flags), (reg), (shift), \
794 #define clk_hw_register_mux_hws(dev, name, parent_hws, num_parents, flags, reg, shift, width, clk_mux_flags, lock) \
795 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, (parent_hws), NULL, (flags), (reg), (shift), \
797 #define clk_hw_register_mux_parent_data(dev, name, parent_data, num_parents, flags, reg, shift, width, clk_mux_flags, \
799 __clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, NULL, (parent_data), (flags), (reg), (shift), \
843 * @mshift: shift to the numerator bit field
845 * @nshift: shift to the denominator bit field
898 * @shift: shift to the multiplier bit field
920 u8 shift;