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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_legalize.c185 struct ir3_register *reg; in legalize_block() local
187 reg = n->dsts[i]; in legalize_block()
189 reg = n->srcs[i - n->dsts_count]; in legalize_block()
191 if (reg_gpr(reg)) { in legalize_block()
197 if (regmask_get(&state->needs_ss, reg)) { in legalize_block()
204 if (regmask_get(&state->needs_sy, reg)) { in legalize_block()
211 foreach_dst (reg, n) { in legalize_block()
212 if (regmask_get(&state->needs_ss_war, reg)) { in legalize_block()
294 foreach_src (reg, n) { in legalize_block()
295 regmask_set(&state->needs_ss_war, reg); in legalize_block()
[all...]
H A Dir3_ra_validate.c123 get_file_size(struct ra_val_ctx *ctx, struct ir3_register *reg) in get_file_size() argument
125 if (reg->flags & IR3_REG_SHARED) in get_file_size()
127 else if (ctx->merged_regs || !(reg->flags & IR3_REG_HALF)) in get_file_size()
208 ra_val_get_file(struct ra_val_ctx *ctx, struct ir3_register *reg) in ra_val_get_file() argument
210 if (reg->flags & IR3_REG_SHARED) in ra_val_get_file()
212 else if (ctx->merged_regs || !(reg->flags & IR3_REG_HALF)) in ra_val_get_file()
/third_party/skia/third_party/externals/swiftshader/src/Shader/
H A DVertexProgram.cpp690 Vector4f reg; in fetchRegister() local
698 reg = r[i]; in fetchRegister()
702 reg = r[i + relativeAddress(src.rel, src.bufferIndex)]; in fetchRegister()
706 reg = r[i + dynamicAddress(src.rel)]; in fetchRegister()
710 reg = readConstant(src, offset); in fetchRegister()
715 reg = v[i]; in fetchRegister()
719 reg = v[i + relativeAddress(src.rel, src.bufferIndex)]; in fetchRegister()
723 reg = v[i + dynamicAddress(src.rel)]; in fetchRegister()
731 reg.x = As<Float4>(Int4(src.integer[0])); in fetchRegister()
732 reg in fetchRegister()
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/third_party/ffmpeg/libavutil/mips/
H A Dcpu.c41 static uint32_t read_cpucfg(uint32_t reg) in read_cpucfg() argument
47 "parse_r reg,%1\n\t" in read_cpucfg()
49 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" in read_cpucfg()
51 :"r"(reg) in read_cpucfg()
/third_party/libunwind/libunwind/src/x86_64/
H A Dunwind_i.h85 extern dwarf_loc_t x86_64_scratch_loc (struct cursor *c, unw_regnum_t reg);
88 extern void *x86_64_r_uc_addr (ucontext_t *uc, int reg);
H A DGget_save_loc.c31 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc) in unw_get_save_loc() argument
38 switch (reg) in unw_get_save_loc()
/third_party/node/deps/v8/src/compiler/backend/x64/
H A Dunwinding-info-writer-x64.h60 BlockInitialState(Register reg, int offset, bool tracking_fp) in BlockInitialState() argument
61 : register_(reg), offset_(offset), tracking_fp_(tracking_fp) {} in BlockInitialState()
/third_party/mesa3d/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_context.h129 unsigned reg = REG_A6XX_CP_SCRATCH_REG(scratch_idx); in emit_marker6() local
132 OUT_PKT4(ring, reg, 1); in emit_marker6()
/third_party/vk-gl-cts/external/vulkan-docs/src/scripts/
H A Djson_h_generator.py96 for feature in self.registry.reg.findall('feature'):
115 allExtensions = self.registry.reg.findall('extensions')
131 typesList = self.registry.reg.findall('types')
/third_party/vixl/test/aarch32/
H A Dtest-utils-aarch32.h118 int32_t reg(unsigned code) const { in reg() function in vixl::aarch32::RegisterDump
154 int32_t spreg() const { return reg(kSPRegNum); }
184 bool Equal32(uint32_t expected, const RegisterDump* core, const Register& reg);
/third_party/mesa3d/src/compiler/nir/
H A Dnir_print.c83 print_register(nir_register *reg, print_state *state) in print_register() argument
86 fprintf(fp, "r%u", reg->index); in print_register()
95 print_register_decl(nir_register *reg, print_state *state) in print_register_decl() argument
98 fprintf(fp, "decl_reg %s %u ", sizes[reg->num_components], reg->bit_size); in print_register_decl()
99 print_register(reg, state); in print_register_decl()
100 if (reg->num_array_elems != 0) in print_register_decl()
101 fprintf(fp, "[%u]", reg->num_array_elems); in print_register_decl()
214 print_register(src->reg, state); in print_reg_src()
215 if (src->reg in print_reg_src()
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/third_party/mesa3d/src/panfrost/bifrost/
H A Dbi_schedule.c84 struct bi_reg_state reg; member
875 bi_tuple_is_new_src(bi_instr *instr, struct bi_reg_state *reg, unsigned src_idx) in bi_tuple_is_new_src() argument
888 for (unsigned t = 0; t < reg->nr_reads; ++t) in bi_tuple_is_new_src()
889 if (bi_is_word_equiv(src, reg->reads[t])) in bi_tuple_is_new_src()
1071 unsigned reg = instr->dest[d].value; in bi_instr_schedulable() local
1076 if (bi_is_equiv(bi_register(reg + d), idx)) in bi_instr_schedulable()
1086 unsigned reg = instr->src[0].value; in bi_instr_schedulable() local
1091 if (bi_is_equiv(bi_register(reg + d), idx)) in bi_instr_schedulable()
1112 unsigned total_writes = tuple->reg.nr_writes; in bi_instr_schedulable()
1124 if (bi_tuple_is_new_src(instr, &tuple->reg, in bi_instr_schedulable()
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/third_party/elfutils/libdw/
H A Dcfi.c60 enough_registers (Dwarf_Word reg, Dwarf_Frame **pfs, int *result) in enough_registers() argument
65 if (unlikely (reg >= INT32_MAX / sizeof ((*pfs)->regs[0]))) in enough_registers()
71 if ((*pfs)->nregs <= reg) in enough_registers()
73 size_t size = offsetof (Dwarf_Frame, regs[reg + 1]); in enough_registers()
84 (reg + 1 - bigger->nregs) * sizeof bigger->regs[0]); in enough_registers()
85 bigger->nregs = reg + 1; in enough_registers()
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_vec4_copy_propagation.cpp502 const unsigned reg = (alloc.offsets[inst->src[i].nr] + in opt_copy_propagation() local
504 const copy_entry &entry = entries[reg]; in opt_copy_propagation()
514 const int reg = in opt_copy_propagation() local
522 entries[reg].saturatemask &= ~inst->dst.writemask; in opt_copy_propagation()
525 entries[reg].value[i] = direct_copy ? &inst->src[0] : NULL; in opt_copy_propagation()
526 entries[reg].saturatemask |= in opt_copy_propagation()
H A Dbrw_vec4_tcs.cpp54 int reg = 0; in setup_payload() local
60 reg++; in setup_payload()
65 reg += 4; in setup_payload()
68 reg = setup_uniforms(reg); in setup_payload()
70 this->first_non_payload_grf = reg; in setup_payload()
/third_party/node/deps/v8/src/maglev/
H A Dmaglev-graph-builder.h273 ValueNode* GetTaggedValue(interpreter::Register reg) { in GetTaggedValue() argument
276 ValueNode* value = current_interpreter_frame_.get(reg); in GetTaggedValue()
283 current_interpreter_frame_.set(reg, tagged); in GetTaggedValue()
287 ValueNode* GetSmiUntaggedValue(interpreter::Register reg) { in GetSmiUntaggedValue() argument
290 ValueNode* value = current_interpreter_frame_.get(reg); in GetSmiUntaggedValue()
295 current_interpreter_frame_.set(reg, untagged); in GetSmiUntaggedValue()
/third_party/mesa3d/src/panfrost/midgard/
H A Dcompiler.h471 assert(!src->reg.indirect); in nir_src_index()
472 return (src->reg.reg->index << 1) | PAN_IS_REG; in nir_src_index()
482 assert(!dst->reg.indirect); in nir_dest_index()
483 return (dst->reg.reg->index << 1) | PAN_IS_REG; in nir_dest_index()
/third_party/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_program_print.c283 unsigned int reg; in rc_print_normal_instruction() local
306 for(reg = 0; reg < opcode->NumSrcRegs; ++reg) { in rc_print_normal_instruction()
307 if (reg > 0) in rc_print_normal_instruction()
310 rc_print_src_register(f, inst, inst->U.I.SrcReg[reg]); in rc_print_normal_instruction()
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp280 unsigned reg = globalRegs[i]; in EmitFunctionBodyStart() local
281 if (MRI.use_empty(reg)) in EmitFunctionBodyStart()
284 if (reg == SP::G6 || reg == SP::G7) in EmitFunctionBodyStart()
285 getTargetStreamer().emitSparcRegisterIgnore(reg); in EmitFunctionBodyStart()
287 getTargetStreamer().emitSparcRegisterScratch(reg); in EmitFunctionBodyStart()
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_lowering_nvc0.cpp437 int minGPR = texi->def(0).rep()->reg.data.id; in findFirstUses()
438 int maxGPR = minGPR + texi->def(0).rep()->reg.size / 4 - 1; in findFirstUses()
469 def->reg.data.id + def->reg.size / 4 - 1 < minGPR || in findFirstUsesBB()
470 def->reg.data.id > maxGPR) in findFirstUsesBB()
479 src->reg.data.id + src->reg.size / 4 - 1 < minGPR || in findFirstUsesBB()
480 src->reg.data.id > maxGPR) in findFirstUsesBB()
697 rZero->reg.data.id = (prog->getTarget()->getChipset() >= NVISA_GK20A_CHIPSET) ? 255 : 63; in visit()
698 carry->reg in visit()
[all...]
/third_party/mesa3d/src/amd/compiler/
H A Daco_insert_NOPs.cpp214 handle_raw_hazard_instr(aco_ptr<Instruction>& pred, PhysReg reg, int* nops_needed, uint32_t* mask) in handle_raw_hazard_instr() argument
220 if (regs_intersect(reg, mask_size, def.physReg(), def.size())) { in handle_raw_hazard_instr()
221 unsigned start = def.physReg() > reg ? def.physReg() - reg : 0; in handle_raw_hazard_instr()
243 handle_raw_hazard_internal(State& state, Block* block, int nops_needed, PhysReg reg, uint32_t mask, in handle_raw_hazard_internal() argument
252 if (handle_raw_hazard_instr<Valu, Vintrp, Salu>(instr, reg, &nops_needed, &mask)) in handle_raw_hazard_internal()
257 if (handle_raw_hazard_instr<Valu, Vintrp, Salu>(block->instructions[pred_idx], reg, in handle_raw_hazard_internal()
270 state, &state.program->blocks[lin_pred], nops_needed, reg, mask, true)); in handle_raw_hazard_internal()
535 unsigned reg = sopk.imm & 0x3f; in handle_instruction_gfx6() local
538 if (reg in handle_instruction_gfx6()
[all...]
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_state.c491 iris_load_register_imm32(struct iris_batch *batch, uint32_t reg, in iris_load_register_imm32() argument
496 mi_store(&b, mi_reg32(reg), mi_imm(val)); in iris_load_register_imm32()
500 iris_load_register_imm64(struct iris_batch *batch, uint32_t reg, in iris_load_register_imm64() argument
505 mi_store(&b, mi_reg64(reg), mi_imm(val)); in iris_load_register_imm64()
512 iris_load_register_mem32(struct iris_batch *batch, uint32_t reg, in iris_load_register_mem32() argument
519 mi_store(&b, mi_reg32(reg), src); in iris_load_register_mem32()
528 iris_load_register_mem64(struct iris_batch *batch, uint32_t reg, in iris_load_register_mem64() argument
535 mi_store(&b, mi_reg64(reg), src); in iris_load_register_mem64()
540 iris_store_register_mem32(struct iris_batch *batch, uint32_t reg, in iris_store_register_mem32() argument
548 struct mi_value src = mi_reg32(reg); in iris_store_register_mem32()
557 iris_store_register_mem64(struct iris_batch *batch, uint32_t reg, struct iris_bo *bo, uint32_t offset, bool predicated) iris_store_register_mem64() argument
[all...]
/third_party/backends/backend/
H A Dhp4200.c118 getreg (HP4200_Scanner * s, unsigned char reg) in getreg() argument
122 if ((reg > 0x08) && (reg < 0x5b)) in getreg()
123 return (unsigned char) LOBYTE (s->regs[reg]); in getreg()
126 lm9830_read_register (s->fd, reg, &reg_value); in getreg()
132 setreg (HP4200_Scanner * s, unsigned char reg, unsigned char reg_value) in setreg() argument
134 s->regs[reg] = reg_value; /* dirty bit should be clear with this */ in setreg()
135 if ((reg < 0x08) || (reg > 0x5b)) in setreg()
137 lm9830_write_register (s->fd, reg, reg_valu in setreg()
142 setbits(HP4200_Scanner * s, unsigned char reg, unsigned char bitmap) setbits() argument
152 clearbits(HP4200_Scanner * s, unsigned char reg, unsigned char mask) clearbits() argument
[all...]
/third_party/mesa3d/src/freedreno/vulkan/
H A Dtu_lrz.c153 struct tu_reg_value reg) in tu6_write_lrz_reg()
158 tu_cs_emit(cs, reg.reg); in tu6_write_lrz_reg()
159 tu_cs_emit(cs, reg.value); in tu6_write_lrz_reg()
161 tu_cs_emit_pkt4(cs, reg.reg, 1); in tu6_write_lrz_reg()
162 tu_cs_emit(cs, reg.value); in tu6_write_lrz_reg()
152 tu6_write_lrz_reg(struct tu_cmd_buffer *cmd, struct tu_cs *cs, struct tu_reg_value reg) tu6_write_lrz_reg() argument
/third_party/libdrm/tests/amdgpu/
H A Djpeg_tests.c90 #define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \
96 #define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg)
141 static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type,
322 static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, in set_reg_jpeg() argument
325 ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type); in set_reg_jpeg()

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