Lines Matching refs:reg
491 iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
496 mi_store(&b, mi_reg32(reg), mi_imm(val));
500 iris_load_register_imm64(struct iris_batch *batch, uint32_t reg,
505 mi_store(&b, mi_reg64(reg), mi_imm(val));
512 iris_load_register_mem32(struct iris_batch *batch, uint32_t reg,
519 mi_store(&b, mi_reg32(reg), src);
528 iris_load_register_mem64(struct iris_batch *batch, uint32_t reg,
535 mi_store(&b, mi_reg64(reg), src);
540 iris_store_register_mem32(struct iris_batch *batch, uint32_t reg,
548 struct mi_value src = mi_reg32(reg);
557 iris_store_register_mem64(struct iris_batch *batch, uint32_t reg,
565 struct mi_value src = mi_reg64(reg);
686 iris_emit_reg(batch, GENX(SLICE_COMMON_ECO_CHICKEN1), reg) {
687 reg.GLKBarrierMode = value;
688 reg.GLKBarrierModeMask = 1;
761 iris_emit_reg(batch, L3_ALLOCATION_REG, reg) {
763 reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
770 reg.ErrorDetectionBehaviorControl = true;
771 reg.UseFullWays = true;
774 reg.URBAllocation = cfg->n[INTEL_L3P_URB];
775 reg.ROAllocation = cfg->n[INTEL_L3P_RO];
776 reg.DCAllocation = cfg->n[INTEL_L3P_DC];
777 reg.AllAllocation = cfg->n[INTEL_L3P_ALL];
780 reg.L3FullWayAllocationEnable = true;
796 iris_emit_reg(batch, GENX(CS_CHICKEN1), reg) {
797 reg.ReplayMode = enable;
798 reg.ReplayModeMask = true;
1024 iris_emit_reg(batch, GENX(SAMPLER_MODE), reg) {
1025 reg.HeaderlessMessageforPreemptableContexts = 1;
1026 reg.HeaderlessMessageforPreemptableContextsMask = 1;
1030 iris_emit_reg(batch, GENX(HALF_SLICE_CHICKEN7), reg) {
1031 reg.EnabledTexelOffsetPrecisionFix = 1;
1032 reg.EnabledTexelOffsetPrecisionFixMask = 1;
1043 iris_emit_reg(batch, GENX(GT_MODE), reg) {
1044 reg.BindingTableAlignment = BTP_18_8;
1045 reg.BindingTableAlignmentMask = true;
1075 iris_emit_reg(batch, GENX(CS_DEBUG_MODE2), reg) {
1076 reg.CONSTANT_BUFFERAddressOffsetDisable = true;
1077 reg.CONSTANT_BUFFERAddressOffsetDisableMask = true;
1080 iris_emit_reg(batch, GENX(INSTPM), reg) {
1081 reg.CONSTANT_BUFFERAddressOffsetDisable = true;
1082 reg.CONSTANT_BUFFERAddressOffsetDisableMask = true;
1087 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1088 reg.FloatBlendOptimizationEnable = true;
1089 reg.FloatBlendOptimizationEnableMask = true;
1090 reg.MSCRAWHazardAvoidanceBit = true;
1091 reg.MSCRAWHazardAvoidanceBitMask = true;
1092 reg.PartialResolveDisableInVC = true;
1093 reg.PartialResolveDisableInVCMask = true;
1101 iris_emit_reg(batch, GENX(TCCNTLREG), reg) {
1102 reg.L3DataPartialWriteMergingEnable = true;
1103 reg.ColorZPartialWriteMergingEnable = true;
1104 reg.URBPartialWriteMergingEnable = true;
1105 reg.TCDisable = true;
1112 iris_emit_reg(batch, GENX(CACHE_MODE_0), reg) {
1113 reg.DisableRepackingforCompression = true;
1114 reg.DisableRepackingforCompressionMask = true;
1140 iris_emit_reg(batch, GENX(HIZ_CHICKEN), reg) {
1141 reg.HZDepthTestLEGEOptimizationDisable = true;
1142 reg.HZDepthTestLEGEOptimizationDisableMask = true;
1777 iris_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1778 reg.NPPMAFixEnable = enable;
1779 reg.NPEarlyZFailsDisable = enable;
1780 reg.NPPMAFixEnableMask = true;
1781 reg.NPEarlyZFailsDisableMask = true;
5785 iris_emit_reg(batch, GENX(COMMON_SLICE_CHICKEN1), reg) {
5786 reg.HIZPlaneOptimizationdisablebit = is_d16_1x_msaa;
5787 reg.HIZPlaneOptimizationdisablebitMask = true;
8377 iris_emit_reg(batch, GENX(GT_MODE), reg) {
8378 reg.SliceHashing = (devinfo->num_slices > 1 ? slice_hashing[idx] : 0);
8379 reg.SliceHashingMask = (devinfo->num_slices > 1 ? -1 : 0);
8380 reg.SubsliceHashing = subslice_hashing[idx];
8381 reg.SubsliceHashingMask = -1;