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Searched refs:rate (Results 626 - 650 of 3915) sorted by relevance

1...<<21222324252627282930>>...157

/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-pll.c520 unsigned long rate, unsigned long parent_rate) in _get_table_rate()
528 sel->output_rate == rate) in _get_table_rate()
554 unsigned long rate, unsigned long parent_rate) in _calc_rate()
561 if (!rate) in _calc_rate()
567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; in _calc_rate()
570 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; in _calc_rate()
574 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; in _calc_rate()
579 * PLL_P_OUT1 rate is not listed in PLLA table in _calc_rate()
584 pr_err("%s Unexpected reference rate %lu\n", in _calc_rate()
590 for (cfg->output_rate = rate; cf in _calc_rate()
518 _get_table_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _get_table_rate() argument
553 _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _calc_rate() argument
727 _update_pll_cpcon(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) _update_pll_cpcon() argument
751 _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) _program_pll() argument
801 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pll_set_rate() argument
843 clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pll_round_rate() argument
869 u64 rate = parent_rate; clk_pll_recalc_rate() local
1022 u64 rate = parent_rate; clk_plle_recalc_rate() local
1039 unsigned long rate = clk_hw_get_rate(hw); tegra_clk_pll_restore_context() local
1220 _calc_dynamic_ramp_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _calc_dynamic_ramp_rate() argument
1303 _pll_ramp_calc_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _pll_ramp_calc_pll() argument
1328 clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllxc_set_rate() argument
1356 clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pll_ramp_round_rate() argument
1486 clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllc_set_rate() argument
1531 _pllre_calc_rate(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _pllre_calc_rate() argument
1552 clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllre_set_rate() argument
1591 u64 rate = parent_rate; clk_pllre_recalc_rate() local
1601 clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pllre_round_rate() argument
[all...]
H A Dclk-super.c150 unsigned long rate; in clk_super_determine_rate() local
154 rate = super->div_ops->round_rate(div_hw, req->rate, in clk_super_determine_rate()
156 if (rate < 0) in clk_super_determine_rate()
157 return rate; in clk_super_determine_rate()
159 req->rate = rate; in clk_super_determine_rate()
174 static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate, in clk_super_set_rate() argument
182 return super->div_ops->set_rate(div_hw, rate, parent_rate); in clk_super_set_rate()
H A Dclk-periph.c54 unsigned long rate; in clk_periph_determine_rate() local
58 rate = div_ops->round_rate(div_hw, req->rate, &req->best_parent_rate); in clk_periph_determine_rate()
59 if (rate < 0) in clk_periph_determine_rate()
60 return rate; in clk_periph_determine_rate()
62 req->rate = rate; in clk_periph_determine_rate()
66 static int clk_periph_set_rate(struct clk_hw *hw, unsigned long rate, in clk_periph_set_rate() argument
75 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
H A Dclk-tegra20-emc.c101 static int emc_set_rate(struct clk_hw *hw, unsigned long rate, in emc_set_rate() argument
108 div = div_frac_get(rate, parent_rate, 8, 1, 0); in emc_set_rate()
134 unsigned long rate, in emc_set_rate_and_parent()
141 div = div_frac_get(rate, parent_rate, 8, 1, 0); in emc_set_rate_and_parent()
178 emc_rate = emc->round_cb(req->rate, req->min_rate, req->max_rate, in emc_determine_rate()
202 req->rate = emc_rate; in emc_determine_rate()
207 pr_err_once("can't find parent for rate %lu emc_rate %lu\n", in emc_determine_rate()
208 req->rate, emc_rate); in emc_determine_rate()
133 emc_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) emc_set_rate_and_parent() argument
/kernel/linux/linux-5.10/sound/firewire/motu/
H A Dmotu-stream.c28 static int keep_resources(struct snd_motu *motu, unsigned int rate, in keep_resources() argument
52 err = amdtp_motu_set_parameters(stream, rate, midi_ports, in keep_resources()
136 int snd_motu_stream_reserve_duplex(struct snd_motu *motu, unsigned int rate, in snd_motu_stream_reserve_duplex() argument
146 if (rate == 0) in snd_motu_stream_reserve_duplex()
147 rate = curr_rate; in snd_motu_stream_reserve_duplex()
149 if (motu->substreams_counter == 0 || curr_rate != rate) { in snd_motu_stream_reserve_duplex()
156 err = snd_motu_protocol_set_clock_rate(motu, rate); in snd_motu_stream_reserve_duplex()
159 "fail to set sampling rate: %d\n", err); in snd_motu_stream_reserve_duplex()
167 err = keep_resources(motu, rate, &motu->tx_stream); in snd_motu_stream_reserve_duplex()
171 err = keep_resources(motu, rate, in snd_motu_stream_reserve_duplex()
[all...]
H A Dmotu-protocol-v2.c27 static int get_clock_rate(u32 data, unsigned int *rate) in get_clock_rate() argument
33 *rate = snd_motu_clock_rates[index]; in get_clock_rate()
39 unsigned int *rate) in snd_motu_protocol_v2_get_clock_rate()
49 return get_clock_rate(be32_to_cpu(reg), rate); in snd_motu_protocol_v2_get_clock_rate()
53 unsigned int rate) in snd_motu_protocol_v2_set_clock_rate()
61 if (snd_motu_clock_rates[i] == rate) in snd_motu_protocol_v2_set_clock_rate()
185 unsigned int rate; in switch_fetching_mode_spartan() local
193 err = get_clock_rate(*data, &rate); in switch_fetching_mode_spartan()
197 if (src == SND_MOTU_CLOCK_SOURCE_SPH && rate > 48000) in switch_fetching_mode_spartan()
38 snd_motu_protocol_v2_get_clock_rate(struct snd_motu *motu, unsigned int *rate) snd_motu_protocol_v2_get_clock_rate() argument
52 snd_motu_protocol_v2_set_clock_rate(struct snd_motu *motu, unsigned int rate) snd_motu_protocol_v2_set_clock_rate() argument
/kernel/linux/linux-5.10/sound/pci/echoaudio/
H A Dmona_dsp.c196 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
205 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
206 /* Save the rate anyhow */ in set_sample_rate()
207 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
208 chip->sample_rate = rate; in set_sample_rate()
213 if (rate >= 88200) { in set_sample_rate()
248 switch (rate) { in set_sample_rate()
282 "set_sample_rate: %d invalid!\n", rate); in set_sample_rate()
288 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
289 chip->sample_rate = rate; in set_sample_rate()
[all...]
/kernel/linux/linux-5.10/sound/soc/qcom/qdsp6/
H A Dq6afe-clocks.c19 .rate = 19200000, \
42 int rate; member
60 Q6AFE_LPASS_CLK_ROOT_DEFAULT, clk->rate); in clk_q6afe_prepare()
71 static int clk_q6afe_set_rate(struct clk_hw *hw, unsigned long rate, in clk_q6afe_set_rate() argument
76 clk->rate = rate; in clk_q6afe_set_rate()
86 return clk->rate; in clk_q6afe_recalc_rate()
89 static long clk_q6afe_round_rate(struct clk_hw *hw, unsigned long rate, in clk_q6afe_round_rate() argument
92 return rate; in clk_q6afe_round_rate()
/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-bcm-iproc.c85 u64 tmp, multi, rate; in iproc_pwmc_get_state() local
100 rate = clk_get_rate(ip->clk); in iproc_pwmc_get_state()
101 if (rate == 0) { in iproc_pwmc_get_state()
115 state->period = div64_u64(tmp, rate); in iproc_pwmc_get_state()
119 state->duty_cycle = div64_u64(tmp, rate); in iproc_pwmc_get_state()
128 u64 rate; in iproc_pwmc_apply() local
130 rate = clk_get_rate(ip->clk); in iproc_pwmc_apply()
146 value = rate * state->period; in iproc_pwmc_apply()
148 value = rate * state->duty_cycle; in iproc_pwmc_apply()
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-bcm-iproc.c75 u64 tmp, multi, rate; in iproc_pwmc_get_state() local
90 rate = clk_get_rate(ip->clk); in iproc_pwmc_get_state()
91 if (rate == 0) { in iproc_pwmc_get_state()
105 state->period = div64_u64(tmp, rate); in iproc_pwmc_get_state()
109 state->duty_cycle = div64_u64(tmp, rate); in iproc_pwmc_get_state()
120 u64 rate; in iproc_pwmc_apply() local
122 rate = clk_get_rate(ip->clk); in iproc_pwmc_apply()
138 value = rate * state->period; in iproc_pwmc_apply()
140 value = rate * state->duty_cycle; in iproc_pwmc_apply()
H A Dpwm-mtk-disp.c75 u64 div, rate; in mtk_disp_pwm_apply() local
118 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_apply()
119 clk_div = mul_u64_u64_div_u64(state->period, rate, NSEC_PER_SEC) >> in mtk_disp_pwm_apply()
130 period = mul_u64_u64_div_u64(state->period, rate, div); in mtk_disp_pwm_apply()
134 high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); in mtk_disp_pwm_apply()
178 u64 rate, period, high_width; in mtk_disp_pwm_get_state() local
205 rate = clk_get_rate(mdp->clk_main); in mtk_disp_pwm_get_state()
216 state->period = DIV64_U64_ROUND_UP(period * (clk_div + 1) * NSEC_PER_SEC, rate); in mtk_disp_pwm_get_state()
219 rate); in mtk_disp_pwm_get_state()
/kernel/linux/linux-6.6/sound/pci/echoaudio/
H A Dmona_dsp.c198 static int set_sample_rate(struct echoaudio *chip, u32 rate) in set_sample_rate() argument
207 "Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); in set_sample_rate()
208 /* Save the rate anyhow */ in set_sample_rate()
209 chip->comm_page->sample_rate = cpu_to_le32(rate); in set_sample_rate()
210 chip->sample_rate = rate; in set_sample_rate()
215 if (rate >= 88200) { in set_sample_rate()
250 switch (rate) { in set_sample_rate()
284 "set_sample_rate: %d invalid!\n", rate); in set_sample_rate()
290 chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ in set_sample_rate()
291 chip->sample_rate = rate; in set_sample_rate()
[all...]
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-pll.c520 unsigned long rate, unsigned long parent_rate) in _get_table_rate()
528 sel->output_rate == rate) in _get_table_rate()
554 unsigned long rate, unsigned long parent_rate) in _calc_rate()
564 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000; in _calc_rate()
567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000; in _calc_rate()
571 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000; in _calc_rate()
576 * PLL_P_OUT1 rate is not listed in PLLA table in _calc_rate()
581 pr_err("%s Unexpected reference rate %lu\n", in _calc_rate()
587 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
726 unsigned long rate) in _update_pll_cpcon()
518 _get_table_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _get_table_rate() argument
553 _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _calc_rate() argument
724 _update_pll_cpcon(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) _update_pll_cpcon() argument
748 _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate) _program_pll() argument
798 clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pll_set_rate() argument
840 clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pll_round_rate() argument
866 u64 rate = parent_rate; clk_pll_recalc_rate() local
1019 u64 rate = parent_rate; clk_plle_recalc_rate() local
1036 unsigned long rate = clk_hw_get_rate(hw); tegra_clk_pll_restore_context() local
1217 _calc_dynamic_ramp_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _calc_dynamic_ramp_rate() argument
1300 _pll_ramp_calc_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _pll_ramp_calc_pll() argument
1325 clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllxc_set_rate() argument
1353 clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pll_ramp_round_rate() argument
1483 clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllc_set_rate() argument
1528 _pllre_calc_rate(struct tegra_clk_pll *pll, struct tegra_clk_pll_freq_table *cfg, unsigned long rate, unsigned long parent_rate) _pllre_calc_rate() argument
1549 clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_pllre_set_rate() argument
1588 u64 rate = parent_rate; clk_pllre_recalc_rate() local
1598 clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) clk_pllre_round_rate() argument
[all...]
H A Dclk-tegra20-emc.c100 static int emc_set_rate(struct clk_hw *hw, unsigned long rate, in emc_set_rate() argument
107 div = div_frac_get(rate, parent_rate, 8, 1, 0); in emc_set_rate()
133 unsigned long rate, in emc_set_rate_and_parent()
140 div = div_frac_get(rate, parent_rate, 8, 1, 0); in emc_set_rate_and_parent()
177 emc_rate = emc->round_cb(req->rate, req->min_rate, req->max_rate, in emc_determine_rate()
201 req->rate = emc_rate; in emc_determine_rate()
206 pr_err_once("can't find parent for rate %lu emc_rate %lu\n", in emc_determine_rate()
207 req->rate, emc_rate); in emc_determine_rate()
132 emc_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index) emc_set_rate_and_parent() argument
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-fixed-factor.c18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
26 unsigned long long int rate; in clk_factor_recalc_rate() local
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
30 return (unsigned long)rate; in clk_factor_recalc_rate()
33 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, in clk_factor_round_rate() argument
41 best_parent = (rate / fi in clk_factor_round_rate()
48 clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) clk_factor_set_rate() argument
[all...]
/kernel/linux/linux-5.10/drivers/clk/ux500/
H A Dclk-sysctrl.c29 unsigned long rate; member
62 return clk->rate; in clk_sysctrl_recalc_rate()
124 unsigned long rate, in clk_reg_sysctrl()
159 clk->rate = rate; in clk_reg_sysctrl()
200 unsigned long rate, in clk_reg_sysctrl_gate_fixed_rate()
209 rate, enable_delay_us, flags, in clk_reg_sysctrl_gate_fixed_rate()
117 clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags, const struct clk_ops *clk_sysctrl_ops) clk_reg_sysctrl() argument
194 clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags) clk_reg_sysctrl_gate_fixed_rate() argument
/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-efm32.c126 unsigned long rate; in efm32_clocksource_init() local
142 rate = clk_get_rate(clk); in efm32_clocksource_init()
157 DIV_ROUND_CLOSEST(rate, 1024), 200, 16, in efm32_clocksource_init()
184 unsigned long rate; in efm32_clockevent_init() local
201 rate = clk_get_rate(clk); in efm32_clockevent_init()
220 clock_event_ddata.periodic_top = DIV_ROUND_CLOSEST(rate, 1024 * HZ); in efm32_clockevent_init()
223 DIV_ROUND_CLOSEST(rate, 1024), in efm32_clockevent_init()
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-pllv4.c88 static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv4_round_rate() argument
99 if (rate >= round_rate) { in clk_pllv4_round_rate()
106 pr_warn("%s: unable to round rate %lu, parent rate %lu\n", in clk_pllv4_round_rate()
107 clk_hw_get_name(hw), rate, parent_rate); in clk_pllv4_round_rate()
114 temp64 = (u64)(rate - round_rate); in clk_pllv4_round_rate()
148 static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate, in clk_pllv4_set_rate() argument
155 mult = rate / parent_rate; in clk_pllv4_set_rate()
163 temp64 = (u64)(rate - mult * parent_rate); in clk_pllv4_set_rate()
/kernel/linux/linux-5.10/include/linux/
H A Dsh_clk.h29 int (*set_rate)(struct clk *clk, unsigned long rate);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
52 unsigned long rate; member
105 unsigned long rate);
109 unsigned long rate);
112 unsigned int div_max, unsigned long rate);
115 unsigned int mult_max, unsigned long rate);
/kernel/linux/linux-5.10/drivers/watchdog/
H A Dpic32-wdt.c75 unsigned long rate; in pic32_wdt_get_timeout_secs() local
78 rate = clk_get_rate(wdt->clk); in pic32_wdt_get_timeout_secs()
81 pic32_wdt_get_clk_id(wdt), rate); in pic32_wdt_get_timeout_secs()
84 rate >>= 5; in pic32_wdt_get_timeout_secs()
85 if (!rate) in pic32_wdt_get_timeout_secs()
93 period = terminal / rate; in pic32_wdt_get_timeout_secs()
96 rate, terminal, period); in pic32_wdt_get_timeout_secs()
/kernel/linux/linux-6.6/include/linux/
H A Dsh_clk.h29 int (*set_rate)(struct clk *clk, unsigned long rate);
31 long (*round_rate)(struct clk *clk, unsigned long rate);
52 unsigned long rate; member
105 unsigned long rate);
109 unsigned long rate);
112 unsigned int div_max, unsigned long rate);
115 unsigned int mult_max, unsigned long rate);
/kernel/linux/linux-6.6/drivers/clk/ux500/
H A Dclk-sysctrl.c29 unsigned long rate; member
62 return clk->rate; in clk_sysctrl_recalc_rate()
125 unsigned long rate, in clk_reg_sysctrl()
160 clk->rate = rate; in clk_reg_sysctrl()
201 unsigned long rate, in clk_reg_sysctrl_gate_fixed_rate()
210 rate, enable_delay_us, flags, in clk_reg_sysctrl_gate_fixed_rate()
118 clk_reg_sysctrl(struct device *dev, const char *name, const char **parent_names, u8 num_parents, u16 *reg_sel, u8 *reg_mask, u8 *reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags, const struct clk_ops *clk_sysctrl_ops) clk_reg_sysctrl() argument
195 clk_reg_sysctrl_gate_fixed_rate(struct device *dev, const char *name, const char *parent_name, u16 reg_sel, u8 reg_mask, u8 reg_bits, unsigned long rate, unsigned long enable_delay_us, unsigned long flags) clk_reg_sysctrl_gate_fixed_rate() argument
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8186/
H A Dmt8186-misc-control.c147 int rate; in mt8186_sgen_rate_set() local
152 rate = ucontrol->value.integer.value[0]; in mt8186_sgen_rate_set()
154 dev_dbg(afe->dev, "%s(), rate %d\n", __func__, rate); in mt8186_sgen_rate_set()
156 if (rate == afe_priv->sgen_rate) in mt8186_sgen_rate_set()
161 mt8186_sgen_rate_idx[rate] << SINE_MODE_CH1_SFT); in mt8186_sgen_rate_set()
165 mt8186_sgen_rate_idx[rate] << SINE_MODE_CH2_SFT); in mt8186_sgen_rate_set()
167 afe_priv->sgen_rate = rate; in mt8186_sgen_rate_set()
/kernel/linux/linux-5.10/drivers/staging/rtl8188eu/core/
H A Drtw_wlan_util.c79 u8 judge_network_type(struct adapter *padapter, unsigned char *rate) in judge_network_type() argument
88 if (rtw_is_cckratesonly_included(rate)) in judge_network_type()
90 else if (rtw_is_cckrates_included(rate)) in judge_network_type()
98 static unsigned char ratetbl_val_2wifirate(unsigned char rate) in ratetbl_val_2wifirate() argument
100 switch (rate & 0x7f) { in ratetbl_val_2wifirate()
130 static bool is_basicrate(struct adapter *padapter, unsigned char rate) in is_basicrate() argument
140 if (rate == ratetbl_val_2wifirate(val)) in is_basicrate()
150 unsigned char rate; in ratetbl2rateset() local
155 rate = pmlmeext->datarate[i]; in ratetbl2rateset()
157 switch (rate) { in ratetbl2rateset()
188 u8 rate; UpdateBrateTbl() local
210 u8 rate; UpdateBrateTblForSoftAP() local
1044 wifirate2_ratetbl_inx(unsigned char rate) wifirate2_ratetbl_inx() argument
1329 unsigned char *rate = cur_network->SupportedRates; update_wireless_mode() local
[all...]
/kernel/linux/linux-5.10/drivers/clk/loongson1/
H A Dclk-loongson1b.c22 u32 pll, rate; in ls1x_pll_recalc_rate() local
25 rate = 12 + (pll & GENMASK(5, 0)); in ls1x_pll_recalc_rate()
26 rate *= OSC; in ls1x_pll_recalc_rate()
27 rate >>= 1; in ls1x_pll_recalc_rate()
29 return rate; in ls1x_pll_recalc_rate()

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