Lines Matching refs:rate
520 unsigned long rate, unsigned long parent_rate)
528 sel->output_rate == rate)
554 unsigned long rate, unsigned long parent_rate)
561 if (!rate)
567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
570 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
574 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
579 * PLL_P_OUT1 rate is not listed in PLLA table
584 pr_err("%s Unexpected reference rate %lu\n",
590 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
729 unsigned long rate)
744 if (rate >= (pll->params->vco_max >> 1))
752 unsigned long rate)
786 _update_pll_cpcon(pll, cfg, rate);
801 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
810 if (rate != pll->params->fixed_rate) {
811 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
813 pll->params->fixed_rate, rate);
819 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
821 pr_err("%s: Failed to set %s rate %lu\n", __func__,
822 clk_hw_get_name(hw), rate);
835 ret = _program_pll(hw, &cfg, rate);
843 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
850 /* PLLM/MB are used for memory; we do not change rate */
856 if (_get_table_rate(hw, &cfg, rate, *prate) &&
857 pll->params->calc_rate(hw, &cfg, rate, *prate))
869 u64 rate = parent_rate;
908 rate *= cfg.n;
909 do_div(rate, cfg.m);
911 return rate;
1022 u64 rate = parent_rate;
1029 rate *= divn;
1030 do_div(rate, divm);
1031 return rate;
1039 unsigned long rate = clk_hw_get_rate(hw);
1047 clk_pll_set_rate(hw, rate, parent_rate);
1152 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1222 unsigned long rate, unsigned long parent_rate)
1228 if (!rate)
1231 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1233 cfg->output_rate = rate * p;
1290 pr_err("%s: Unexpected reference rate %lu\n",
1305 unsigned long rate, unsigned long parent_rate)
1310 err = _get_table_rate(hw, cfg, rate, parent_rate);
1312 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1328 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1336 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1348 ret = _program_pll(hw, &cfg, rate);
1356 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1364 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1472 pr_err("%s: Unexpected reference rate %lu\n",
1486 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1497 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1533 unsigned long rate, unsigned long parent_rate)
1539 n = rate * m / parent_rate;
1552 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1563 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1591 u64 rate = parent_rate;
1595 rate *= cfg.n;
1596 do_div(rate, cfg.m);
1598 return rate;
1601 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1606 return _pllre_calc_rate(pll, NULL, rate, *prate);
1775 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2126 /* program minimum rate by default */
2233 * minimum VCO rate (the latter assured that shadowed divider settings
2363 /* initialize PLL to minimum rate */