Lines Matching refs:rate

520 			   unsigned long rate, unsigned long parent_rate)
528 sel->output_rate == rate)
554 unsigned long rate, unsigned long parent_rate)
564 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
567 cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
571 cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
576 * PLL_P_OUT1 rate is not listed in PLLA table
581 pr_err("%s Unexpected reference rate %lu\n",
587 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq;
726 unsigned long rate)
741 if (rate >= (pll->params->vco_max >> 1))
749 unsigned long rate)
783 _update_pll_cpcon(pll, cfg, rate);
798 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
807 if (rate != pll->params->fixed_rate) {
808 pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
810 pll->params->fixed_rate, rate);
816 if (_get_table_rate(hw, &cfg, rate, parent_rate) &&
817 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) {
818 pr_err("%s: Failed to set %s rate %lu\n", __func__,
819 clk_hw_get_name(hw), rate);
832 ret = _program_pll(hw, &cfg, rate);
840 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
847 /* PLLM/MB are used for memory; we do not change rate */
853 if (_get_table_rate(hw, &cfg, rate, *prate) &&
854 pll->params->calc_rate(hw, &cfg, rate, *prate))
866 u64 rate = parent_rate;
905 rate *= cfg.n;
906 do_div(rate, cfg.m);
908 return rate;
1019 u64 rate = parent_rate;
1026 rate *= divn;
1027 do_div(rate, divm);
1028 return rate;
1036 unsigned long rate = clk_hw_get_rate(hw);
1044 clk_pll_set_rate(hw, rate, parent_rate);
1149 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
1219 unsigned long rate, unsigned long parent_rate)
1225 if (!rate)
1228 p = DIV_ROUND_UP(pll->params->vco_min, rate);
1230 cfg->output_rate = rate * p;
1287 pr_err("%s: Unexpected reference rate %lu\n",
1302 unsigned long rate, unsigned long parent_rate)
1307 err = _get_table_rate(hw, cfg, rate, parent_rate);
1309 err = _calc_dynamic_ramp_rate(hw, cfg, rate, parent_rate);
1325 static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
1333 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1345 ret = _program_pll(hw, &cfg, rate);
1353 static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
1361 ret = _pll_ramp_calc_pll(hw, &cfg, rate, *prate);
1469 pr_err("%s: Unexpected reference rate %lu\n",
1483 static int clk_pllc_set_rate(struct clk_hw *hw, unsigned long rate,
1494 ret = _pll_ramp_calc_pll(hw, &cfg, rate, parent_rate);
1530 unsigned long rate, unsigned long parent_rate)
1536 n = rate * m / parent_rate;
1549 static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate,
1560 _pllre_calc_rate(pll, &cfg, rate, parent_rate);
1588 u64 rate = parent_rate;
1592 rate *= cfg.n;
1593 do_div(rate, cfg.m);
1595 return rate;
1598 static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
1603 return _pllre_calc_rate(pll, NULL, rate, *prate);
1772 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2123 /* program minimum rate by default */
2230 * minimum VCO rate (the latter assured that shadowed divider settings
2360 /* initialize PLL to minimum rate */