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/kernel/linux/linux-5.10/drivers/net/mdio/
H A Dmdio-bcm-iproc.c38 void __iomem *base; member
41 static inline int iproc_mdio_wait_for_idle(void __iomem *base) in iproc_mdio_wait_for_idle() argument
47 val = readl(base + MII_CTRL_OFFSET); in iproc_mdio_wait_for_idle()
57 static inline void iproc_mdio_config_clk(void __iomem *base) in iproc_mdio_config_clk() argument
63 writel(val, base + MII_CTRL_OFFSET); in iproc_mdio_config_clk()
72 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_read()
83 writel(cmd, priv->base + MII_DATA_OFFSET); in iproc_mdio_read()
85 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_read()
89 cmd = readl(priv->base + MII_DATA_OFFSET) & MII_DATA_MASK; in iproc_mdio_read()
101 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_write()
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/kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_simple_resource.c34 * @base: The TTM base object implementing user-space visibility.
39 struct ttm_base_object base; member
104 ttm_base_object_kfree(usimple, base); in vmw_simple_resource_free()
119 struct ttm_base_object *base = *p_base; in vmw_simple_resource_base_release() local
121 container_of(base, struct vmw_user_simple_resource, base); in vmw_simple_resource_base_release()
191 usimple->base.shareable = false; in vmw_simple_resource_create_ioctl()
192 usimple->base.tfile = NULL; in vmw_simple_resource_create_ioctl()
203 ret = ttm_base_object_init(tfile, &usimple->base, fals in vmw_simple_resource_create_ioctl()
237 struct ttm_base_object *base; vmw_simple_resource_lookup() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c42 ddc->base.base.ctx
51 dal_hw_gpio_destruct(&pin->base); in dal_hw_ddc_destruct()
77 hw_gpio = &ddc->base; in set_config()
95 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { in set_config()
97 if (hw_gpio->base.en == GPIO_DDC_LINE_DDC_VGA) { in set_config()
173 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && in set_config()
174 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { in set_config()
183 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && in set_config()
184 (hw_gpio->base in set_config()
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/kernel/linux/linux-6.6/drivers/net/mdio/
H A Dmdio-bcm-iproc.c38 void __iomem *base; member
41 static inline int iproc_mdio_wait_for_idle(void __iomem *base) in iproc_mdio_wait_for_idle() argument
47 val = readl(base + MII_CTRL_OFFSET); in iproc_mdio_wait_for_idle()
57 static inline void iproc_mdio_config_clk(void __iomem *base) in iproc_mdio_config_clk() argument
63 writel(val, base + MII_CTRL_OFFSET); in iproc_mdio_config_clk()
72 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_read()
83 writel(cmd, priv->base + MII_DATA_OFFSET); in iproc_mdio_read()
85 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_read()
89 cmd = readl(priv->base + MII_DATA_OFFSET) & MII_DATA_MASK; in iproc_mdio_read()
101 rc = iproc_mdio_wait_for_idle(priv->base); in iproc_mdio_write()
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/third_party/gn/src/gn/
H A Dbuild_settings.h14 #include "base/files/file_path.h"
49 const base::FilePath& root_path() const { return root_path_; } in root_path()
50 const base::FilePath& dotfile_name() const { return dotfile_name_; } in dotfile_name()
52 void SetRootPath(const base::FilePath& r);
53 void set_dotfile_name(const base::FilePath& d) { dotfile_name_ = d; } in set_dotfile_name()
58 const base::FilePath& secondary_source_path() const { in secondary_source_path()
64 base::FilePath python_path() const { return python_path_; } in python_path()
65 void set_python_path(const base::FilePath& p) { python_path_ = p; } in set_python_path()
114 base::FilePath GetFullPath(const SourceFile& file) const;
115 base
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/third_party/node/deps/v8/third_party/zlib/google/
H A Dcompression_utils.cc7 #include "base/bit_cast.h"
8 #include "base/check_op.h"
9 #include "base/process/memory.h"
10 #include "base/sys_byteorder.h"
16 bool GzipCompress(base::span<const char> input, in GzipCompress()
37 bool GzipCompress(base::span<const char> input, std::string* output) { in GzipCompress()
38 return GzipCompress(base::as_bytes(input), output); in GzipCompress()
41 bool GzipCompress(base::span<const uint8_t> input, std::string* output) { in GzipCompress()
51 if (!base::UncheckedMalloc(compressed_data_size, in GzipCompress()
93 bool GzipUncompress(base
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H A Dzip_writer.cc9 #include "base/files/file.h"
10 #include "base/logging.h"
11 #include "base/strings/strcat.h"
12 #include "base/strings/string_util.h"
23 const base::TimeTicks now = base::TimeTicks::Now(); in ShouldContinue()
35 bool ZipWriter::AddFileContent(const base::FilePath& path, base::File file) { in AddFileContent()
62 bool ZipWriter::OpenNewFileEntry(const base::FilePath& path, in OpenNewFileEntry()
64 base in OpenNewFileEntry()
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/third_party/skia/third_party/externals/zlib/google/
H A Dcompression_utils.cc7 #include "base/bit_cast.h"
8 #include "base/check_op.h"
9 #include "base/process/memory.h"
10 #include "base/sys_byteorder.h"
16 bool GzipCompress(base::span<const char> input, in GzipCompress()
37 bool GzipCompress(base::span<const char> input, std::string* output) { in GzipCompress()
38 return GzipCompress(base::as_bytes(input), output); in GzipCompress()
41 bool GzipCompress(base::span<const uint8_t> input, std::string* output) { in GzipCompress()
51 if (!base::UncheckedMalloc(compressed_data_size, in GzipCompress()
93 bool GzipUncompress(base
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/third_party/mesa3d/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_bo.c147 return ((struct amdgpu_winsys_bo*)buf)->base.placement; in amdgpu_bo_get_initial_domain()
153 return ((struct amdgpu_winsys_bo*)buf)->base.usage; in amdgpu_bo_get_flags()
175 amdgpu_bo_unmap(&ws->dummy_ws.base, &bo->base); in amdgpu_bo_destroy()
210 if (bo->base.placement & RADEON_DOMAIN_VRAM_GTT) { in amdgpu_bo_destroy()
211 amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP); in amdgpu_bo_destroy()
218 if (bo->base.placement & RADEON_DOMAIN_VRAM) in amdgpu_bo_destroy()
219 ws->allocated_vram -= align64(bo->base.size, ws->info.gart_page_size); in amdgpu_bo_destroy()
220 else if (bo->base.placement & RADEON_DOMAIN_GTT) in amdgpu_bo_destroy()
221 ws->allocated_gtt -= align64(bo->base in amdgpu_bo_destroy()
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/kernel/linux/linux-5.10/arch/mips/include/asm/netlogic/xlr/
H A Dpic.h223 nlm_pic_enable_irt(uint64_t base, int irt) in nlm_pic_enable_irt() argument
227 reg = nlm_read_reg(base, PIC_IRT_1(irt)); in nlm_pic_enable_irt()
228 nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); in nlm_pic_enable_irt()
232 nlm_pic_disable_irt(uint64_t base, int irt) in nlm_pic_disable_irt() argument
236 reg = nlm_read_reg(base, PIC_IRT_1(irt)); in nlm_pic_disable_irt()
237 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); in nlm_pic_disable_irt()
241 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) in nlm_pic_send_ipi() argument
247 nlm_write_reg(base, PIC_IPI, in nlm_pic_send_ipi()
252 nlm_pic_ack(uint64_t base, int irt) in nlm_pic_ack() argument
254 nlm_write_reg(base, PIC_INT_AC in nlm_pic_ack()
258 nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt, int en) nlm_pic_init_irt() argument
267 nlm_pic_read_timer(uint64_t base, int timer) nlm_pic_read_timer() argument
282 nlm_pic_read_timer32(uint64_t base, int timer) nlm_pic_read_timer32() argument
288 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) nlm_pic_set_timer() argument
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/kernel/linux/linux-5.10/drivers/media/platform/mtk-vcodec/
H A Dvenc_vpu_if.c172 out.base.msg_id = AP_IPIMSG_ENC_SET_PARAM; in vpu_enc_set_param()
173 out.base.vpu_inst_addr = vpu->inst_addr; in vpu_enc_set_param()
174 out.base.param_id = id; in vpu_enc_set_param()
178 out.base.data_item = 3; in vpu_enc_set_param()
179 out.base.data[0] = in vpu_enc_set_param()
181 out.base.data[1] = in vpu_enc_set_param()
183 out.base.data[2] = venc_enc_param_num_mb(enc_param); in vpu_enc_set_param()
185 out.base.data_item = 0; in vpu_enc_set_param()
189 out.base.data_item = 0; in vpu_enc_set_param()
192 out.base in vpu_enc_set_param()
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/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-nforce2.c56 int base; member
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
78 #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
79 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
81 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
84 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
323 smbus->base in nforce2_probe_smb()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/selftests/
H A Di915_active.c18 struct i915_active base; member
30 i915_active_fini(&active->base); in __live_free()
46 static int __live_active(struct i915_active *base) in __live_active() argument
48 struct live_active *active = container_of(base, typeof(*active), base); in __live_active()
54 static void __live_retire(struct i915_active *base) in __live_retire() argument
56 struct live_active *active = container_of(base, typeof(*active), base); in __live_retire()
71 i915_active_init(&active->base, __live_active, __live_retire); in __live_alloc()
95 err = i915_active_acquire(&active->base); in __live_active_setup()
[all...]
/kernel/linux/linux-5.10/drivers/nvmem/
H A Dsprd-efuse.c68 void __iomem *base; member
108 u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
115 writel(val, efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
125 writel(val, efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
133 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_read_power()
140 writel(val, efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_read_power()
148 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_prog_lock()
155 writel(val, efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_prog_lock()
160 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_auto_check()
167 writel(val, efuse->base in sprd_efuse_set_auto_check()
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H A Drockchip-efuse.c51 void __iomem *base; member
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
79 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
81 *buf++ = readb(efuse->base + REG_EFUSE_DOUT); in rockchip_rk3288_efuse_read()
82 writel(readl(efuse->base in rockchip_rk3288_efuse_read()
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/kernel/linux/linux-6.6/drivers/clk/mediatek/
H A Dclk-pllfh.c64 void __iomem *base; in fhctl_parse_dt() local
75 base = of_iomap(node, 0); in fhctl_parse_dt()
76 if (!base) { in fhctl_parse_dt()
103 pllfh->state.base = base; in fhctl_parse_dt()
110 iounmap(base); in fhctl_parse_dt()
119 void __iomem *base = pllfh_data->state.base; in pllfh_init() local
120 void __iomem *fhx_base = base + pllfh_data->data.fhx_offset; in pllfh_init()
126 regs->reg_hp_en = base in pllfh_init()
152 mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data, struct mtk_pllfh_data *pllfh_data, void __iomem *base) mtk_clk_register_pllfh() argument
202 void __iomem *base; mtk_clk_register_pllfhs() local
264 void __iomem *base = NULL, *fhctl_base = NULL; mtk_clk_unregister_pllfhs() local
[all...]
/kernel/linux/linux-6.6/drivers/nvmem/
H A Dsprd-efuse.c68 void __iomem *base; member
108 u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
115 writel(val, efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
125 writel(val, efuse->base + SPRD_EFUSE_PW_SWT); in sprd_efuse_set_prog_power()
133 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_read_power()
140 writel(val, efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_read_power()
148 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_prog_lock()
155 writel(val, efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_prog_lock()
160 u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); in sprd_efuse_set_auto_check()
167 writel(val, efuse->base in sprd_efuse_set_auto_check()
[all...]
H A Drockchip-efuse.c51 void __iomem *base; member
68 writel(RK3288_LOAD | RK3288_PGENB, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
71 writel(readl(efuse->base + REG_EFUSE_CTRL) & in rockchip_rk3288_efuse_read()
73 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
74 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
76 efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
78 writel(readl(efuse->base + REG_EFUSE_CTRL) | in rockchip_rk3288_efuse_read()
79 RK3288_STROBE, efuse->base + REG_EFUSE_CTRL); in rockchip_rk3288_efuse_read()
81 *buf++ = readb(efuse->base + REG_EFUSE_DOUT); in rockchip_rk3288_efuse_read()
82 writel(readl(efuse->base in rockchip_rk3288_efuse_read()
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/kernel/linux/linux-6.6/drivers/perf/hisilicon/
H A Dhisi_uncore_cpa_pmu.c52 return readq(cpa_pmu->base + hisi_cpa_pmu_get_counter_offset(hwc->idx)); in hisi_cpa_pmu_read_counter()
58 writeq(val, cpa_pmu->base + hisi_cpa_pmu_get_counter_offset(hwc->idx)); in hisi_cpa_pmu_write_counter()
78 val = readl(cpa_pmu->base + reg); in hisi_cpa_pmu_write_evtype()
81 writel(val, cpa_pmu->base + reg); in hisi_cpa_pmu_write_evtype()
88 val = readl(cpa_pmu->base + CPA_PERF_CTRL); in hisi_cpa_pmu_start_counters()
90 writel(val, cpa_pmu->base + CPA_PERF_CTRL); in hisi_cpa_pmu_start_counters()
97 val = readl(cpa_pmu->base + CPA_PERF_CTRL); in hisi_cpa_pmu_stop_counters()
99 writel(val, cpa_pmu->base + CPA_PERF_CTRL); in hisi_cpa_pmu_stop_counters()
106 val = readl(cpa_pmu->base + CPA_CFG_REG); in hisi_cpa_pmu_disable_pm()
108 writel(val, cpa_pmu->base in hisi_cpa_pmu_disable_pm()
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
H A Ddp_parser.c28 void __iomem *base; in dp_ioremap() local
30 base = devm_platform_get_and_ioremap_resource(pdev, idx, &res); in dp_ioremap()
31 if (!IS_ERR(base)) in dp_ioremap()
34 return base; in dp_ioremap()
43 dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); in dp_parser_ctrl_res()
44 if (IS_ERR(dss->ahb.base)) in dp_parser_ctrl_res()
45 return PTR_ERR(dss->ahb.base); in dp_parser_ctrl_res()
47 dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); in dp_parser_ctrl_res()
48 if (IS_ERR(dss->aux.base)) { in dp_parser_ctrl_res()
56 if (PTR_ERR(dss->aux.base) in dp_parser_ctrl_res()
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/kernel/linux/linux-6.6/drivers/gpu/drm/i915/selftests/
H A Di915_active.c19 struct i915_active base; member
31 i915_active_fini(&active->base); in __live_free()
47 static int __live_active(struct i915_active *base) in __live_active() argument
49 struct live_active *active = container_of(base, typeof(*active), base); in __live_active()
55 static void __live_retire(struct i915_active *base) in __live_retire() argument
57 struct live_active *active = container_of(base, typeof(*active), base); in __live_retire()
72 i915_active_init(&active->base, __live_active, __live_retire, 0); in __live_alloc()
96 err = i915_active_acquire(&active->base); in __live_active_setup()
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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-replicator.c31 * @base: memory mapped base address for this component. Also indicates
39 void __iomem *base; member
50 CS_UNLOCK(drvdata->base); in dynamic_replicator_reset()
53 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); in dynamic_replicator_reset()
54 writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); in dynamic_replicator_reset()
58 CS_LOCK(drvdata->base); in dynamic_replicator_reset()
66 if (drvdata->base) in replicator_reset()
77 CS_UNLOCK(drvdata->base); in dynamic_replicator_enable()
79 id0val = readl_relaxed(drvdata->base in dynamic_replicator_enable()
224 void __iomem *base; replicator_probe() local
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/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-nforce2.c56 int base; member
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
78 #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
79 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
81 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
84 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
323 smbus->base in nforce2_probe_smb()
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/third_party/node/deps/zlib/google/
H A Dzip_writer.cc9 #include "base/files/file.h"
10 #include "base/logging.h"
11 #include "base/strings/strcat.h"
12 #include "base/strings/string_util.h"
23 const base::TimeTicks now = base::TimeTicks::Now(); in ShouldContinue()
35 bool ZipWriter::AddFileContent(const base::FilePath& path, base::File file) { in AddFileContent()
62 bool ZipWriter::OpenNewFileEntry(const base::FilePath& path, in OpenNewFileEntry()
64 base in OpenNewFileEntry()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv30/
H A Dnv30_context.c46 screen = &nv30->screen->base; in nv30_context_kick_notify()
76 struct nouveau_pushbuf *push = nv30->base.pushbuf; in nv30_context_flush()
79 nouveau_fence_ref(nv30->screen->base.fence.current, in nv30_context_flush()
84 nouveau_context_update_frame_stats(&nv30->base); in nv30_context_flush()
162 if (nv30->base.pipe.stream_uploader) in nv30_context_destroy()
163 u_upload_destroy(nv30->base.pipe.stream_uploader); in nv30_context_destroy()
171 if (nv30->screen->base.pushbuf->user_priv == &nv30->bufctx) in nv30_context_destroy()
172 nv30->screen->base.pushbuf->user_priv = NULL; in nv30_context_destroy()
179 nouveau_context_destroy(&nv30->base); in nv30_context_destroy()
202 nv30->base in nv30_context_create()
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