Lines Matching refs:base
56 int base;
74 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
75 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
76 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
77 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
78 #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
79 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
81 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
84 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
323 smbus->base = pci_resource_start(dev, bar);
324 if (smbus->base) {
337 smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
341 error = acpi_check_region(smbus->base, smbus->size,
346 if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
348 smbus->base, smbus->base+smbus->size-1, name);
357 "SMBus nForce2 adapter at %04x", smbus->base);
361 release_region(smbus->base, smbus->size);
365 smbus->base);
394 smbuses[0].base = 0; /* to have a check value */
400 smbuses[1].base = 0;
405 smbuses[1].base = 0; /* to have a check value */
424 if (smbuses[0].base) {
426 release_region(smbuses[0].base, smbuses[0].size);
428 if (smbuses[1].base) {
430 release_region(smbuses[1].base, smbuses[1].size);