| /kernel/linux/linux-6.6/drivers/i2c/busses/ |
| H A D | i2c-axxia.c | 122 * @base: pointer to register struct
136 void __iomem *base; member
156 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_disable()
157 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable()
164 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_enable()
165 writel(int_en | mask, idev->base + MST_INT_ENABLE); in i2c_int_enable()
190 writel(0x01, idev->base + SOFT_RESET); in axxia_i2c_init()
192 while (readl(idev->base + SOFT_RESET) & 1) { in axxia_i2c_init()
200 writel(0x1, idev->base + GLOBAL_CONTROL); in axxia_i2c_init()
215 writel(t_high, idev->base in axxia_i2c_init()
737 void __iomem *base; axxia_i2c_probe() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dccg.c | 31 container_of(dccg, struct dcn_dccg, base)
41 dccg_dcn->base.ctx
59 struct dccg *base; in dccg3_create() local
66 base = &dccg_dcn->base; in dccg3_create()
67 base->ctx = ctx; in dccg3_create()
68 base->funcs = &dccg3_funcs; in dccg3_create()
74 return &dccg_dcn->base; in dccg3_create()
84 struct dccg *base; in dccg30_create() local
91 base in dccg30_create()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gem/ |
| H A D | i915_gem_clflush.c | 15 struct dma_fence_work base; member
27 static int clflush_work(struct dma_fence_work *base) in clflush_work() argument
29 struct clflush *clflush = container_of(base, typeof(*clflush), base); in clflush_work()
43 static void clflush_release(struct dma_fence_work *base) in clflush_release() argument
45 struct clflush *clflush = container_of(base, typeof(*clflush), base); in clflush_release()
66 dma_fence_work_init(&clflush->base, &clflush_ops); in clflush_work_create()
109 i915_sw_fence_await_reservation(&clflush->base.chain, in i915_gem_clflush_object()
110 obj->base in i915_gem_clflush_object()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| H A D | intel_lrc.h | 38 #define RING_ELSP(base) _MMIO((base) + 0x230)
39 #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
40 #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
41 #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
47 #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base)
[all...] |
| /kernel/linux/linux-5.10/drivers/remoteproc/ |
| H A D | qcom_pil_info.c | 16 * region followed by a 64 bit base address and 32 bit size, both little
23 void __iomem *base; member
34 void __iomem *base; in qcom_pil_info_init() local
38 if (_reloc.base) in qcom_pil_info_init()
50 base = ioremap(imem.start, resource_size(&imem)); in qcom_pil_info_init()
51 if (!base) { in qcom_pil_info_init()
56 memset_io(base, 0, resource_size(&imem)); in qcom_pil_info_init()
58 _reloc.base = base; in qcom_pil_info_init()
67 * @base
72 qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) qcom_pil_info_store() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/remoteproc/ |
| H A D | qcom_pil_info.c | 16 * region followed by a 64 bit base address and 32 bit size, both little
23 void __iomem *base; member
34 void __iomem *base; in qcom_pil_info_init() local
38 if (_reloc.base) in qcom_pil_info_init()
50 base = ioremap(imem.start, resource_size(&imem)); in qcom_pil_info_init()
51 if (!base) { in qcom_pil_info_init()
56 memset_io(base, 0, resource_size(&imem)); in qcom_pil_info_init()
58 _reloc.base = base; in qcom_pil_info_init()
67 * @base
72 qcom_pil_info_store(const char *image, phys_addr_t base, size_t size) qcom_pil_info_store() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dccg.c | 31 container_of(dccg, struct dcn_dccg, base)
41 dccg_dcn->base.ctx
62 struct dccg *base; in dccg3_create() local
69 base = &dccg_dcn->base; in dccg3_create()
70 base->ctx = ctx; in dccg3_create()
71 base->funcs = &dccg3_funcs; in dccg3_create()
77 return &dccg_dcn->base; in dccg3_create()
87 struct dccg *base; in dccg30_create() local
94 base in dccg30_create()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_resource.c | 496 return &ipp->base; in dcn21_ipp_create()
511 return &dpp->base; in dcn21_dpp_create()
535 return &aux_engine->base; in dcn21_aux_engine_create()
683 for (i = 0; i < pool->base.stream_enc_count; i++) { in dcn21_resource_destruct()
684 if (pool->base.stream_enc[i] != NULL) { in dcn21_resource_destruct()
685 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); in dcn21_resource_destruct()
686 pool->base.stream_enc[i] = NULL; in dcn21_resource_destruct()
690 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
691 if (pool->base.dscs[i] != NULL) in dcn21_resource_destruct()
692 dcn20_dsc_destroy(&pool->base in dcn21_resource_destruct()
[all...] |
| /kernel/linux/linux-6.6/include/crypto/internal/ |
| H A D | aead.h | 22 char head[offsetof(struct aead_alg, base)];
23 struct crypto_instance base; member
30 struct crypto_spawn base; member
34 struct crypto_queue base; member
39 return crypto_tfm_ctx(&tfm->base); in crypto_aead_ctx()
44 return crypto_tfm_ctx_dma(&tfm->base); in crypto_aead_ctx_dma()
50 return container_of(&inst->alg.base, struct crypto_instance, alg); in aead_crypto_instance()
55 return container_of(&inst->alg, struct aead_instance, alg.base); in aead_instance()
60 return aead_instance(crypto_tfm_alg_instance(&aead->base)); in aead_alg_instance()
85 crypto_request_complete(&req->base, er in aead_request_complete()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_dspp.c | 29 u32 base; in dpu_setup_dspp_pcc() local
36 base = ctx->cap->sblk->pcc.base; in dpu_setup_dspp_pcc()
38 if (!base) { in dpu_setup_dspp_pcc()
39 DRM_ERROR("invalid ctx %pK pcc base 0x%x\n", ctx, base); in dpu_setup_dspp_pcc()
45 DPU_REG_WRITE(&ctx->hw, base, PCC_DIS); in dpu_setup_dspp_pcc()
49 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_R_OFF, cfg->r.r); in dpu_setup_dspp_pcc()
50 DPU_REG_WRITE(&ctx->hw, base + PCC_RED_G_OFF, cfg->r.g); in dpu_setup_dspp_pcc()
51 DPU_REG_WRITE(&ctx->hw, base in dpu_setup_dspp_pcc()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_simple_resource.c | 34 * @base: The TTM base object implementing user-space visibility.
38 struct ttm_base_object base; member
100 ttm_base_object_kfree(usimple, base); in vmw_simple_resource_free()
114 struct ttm_base_object *base = *p_base; in vmw_simple_resource_base_release() local
116 container_of(base, struct vmw_user_simple_resource, base); in vmw_simple_resource_base_release()
161 usimple->base.shareable = false; in vmw_simple_resource_create_ioctl()
162 usimple->base.tfile = NULL; in vmw_simple_resource_create_ioctl()
173 ret = ttm_base_object_init(tfile, &usimple->base, fals in vmw_simple_resource_create_ioctl()
207 struct ttm_base_object *base; vmw_simple_resource_lookup() local
[all...] |
| H A D | vmwgfx_fence.c | 51 struct ttm_base_object base; member
82 return container_of(fence->base.lock, struct vmw_fence_manager, lock); in fman_from_fence()
126 container_of(f, struct vmw_fence_obj, base); in vmw_fence_obj_destroy()
150 container_of(f, struct vmw_fence_obj, base); in vmw_fence_enable_signaling()
156 if (seqno - fence->base.seqno < VMW_FENCE_WRAP) in vmw_fence_enable_signaling()
163 struct dma_fence_cb base; member
171 container_of(cb, struct vmwgfx_wait_cb, base); in vmwgfx_wait_cb()
181 container_of(f, struct vmw_fence_obj, base); in vmw_fence_wait()
203 cb.base.func = vmwgfx_wait_cb; in vmw_fence_wait()
205 list_add(&cb.base in vmw_fence_wait()
575 struct ttm_base_object *base = *p_base; vmw_user_fence_base_release() local
704 struct ttm_base_object *base = ttm_base_object_lookup(tfile, handle); vmw_fence_obj_lookup() local
729 struct ttm_base_object *base; vmw_fence_obj_wait_ioctl() local
782 struct ttm_base_object *base; vmw_fence_obj_signaled_ioctl() local
971 struct drm_pending_event base; global() member
1049 struct ttm_base_object *base = vmw_fence_event_ioctl() local
[all...] |
| /kernel/linux/linux-5.10/drivers/crypto/ux500/cryp/ |
| H A D | cryp.c | 29 * @device_data: Pointer to the device data struct for base address.
38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); in cryp_check()
45 readl_relaxed(&device_data->base->periphId0)) in cryp_check()
47 readl_relaxed(&device_data->base->periphId1)) in cryp_check()
49 readl_relaxed(&device_data->base->periphId3)) in cryp_check()
51 readl_relaxed(&device_data->base->pcellId0)) in cryp_check()
53 readl_relaxed(&device_data->base->pcellId1)) in cryp_check()
55 readl_relaxed(&device_data->base->pcellId2)) in cryp_check()
57 readl_relaxed(&device_data->base->pcellId3))) { in cryp_check()
66 * @device_data: Pointer to the device data struct for base addres
[all...] |
| /kernel/linux/linux-5.10/drivers/watchdog/ |
| H A D | imx7ulp_wdt.c | 51 void __iomem *base; member
55 static int imx7ulp_wdt_wait(void __iomem *base, u32 mask) in imx7ulp_wdt_wait() argument
57 u32 val = readl(base + WDOG_CS); in imx7ulp_wdt_wait()
59 if (!(val & mask) && readl_poll_timeout_atomic(base + WDOG_CS, val, in imx7ulp_wdt_wait()
71 u32 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
75 writel(UNLOCK, wdt->base + WDOG_CNT); in imx7ulp_wdt_enable()
76 ret = imx7ulp_wdt_wait(wdt->base, WDOG_CS_ULK); in imx7ulp_wdt_enable()
80 writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
82 writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
83 imx7ulp_wdt_wait(wdt->base, WDOG_CS_RC in imx7ulp_wdt_enable()
91 imx7ulp_wdt_is_enabled(void __iomem *base) imx7ulp_wdt_is_enabled() argument
176 imx7ulp_wdt_init(void __iomem *base, unsigned int timeout) imx7ulp_wdt_init() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| H A D | anx9805.c | 24 #define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
25 #define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
26 #define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
31 struct nvkm_i2c_pad base; member
37 struct nvkm_i2c_bus base; member
43 anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) in anx9805_bus_xfer() argument
45 struct anx9805_bus *bus = anx9805_bus(base); in anx9805_bus_xfer()
103 anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, in anx9805_bus_new() argument
106 struct anx9805_pad *pad = anx9805_pad(base); in anx9805_bus_new()
112 *pbus = &bus->base; in anx9805_bus_new()
130 struct nvkm_i2c_aux base; global() member
136 anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, u8 type, u32 addr, u8 *data, u8 *size) anx9805_aux_xfer() argument
192 anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, int link_nr, int link_bw, bool enh) anx9805_aux_lnk_ctl() argument
232 anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, struct nvkm_i2c_aux **pbus) anx9805_aux_new() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | nv50.c | 32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init() argument
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) nv50_bar_bar2_vmm() argument
85 nv50_bar_bar2_init(struct nvkm_bar *base) nv50_bar_bar2_init() argument
95 nv50_bar_init(struct nvkm_bar *base) nv50_bar_init() argument
106 nv50_bar_oneinit(struct nvkm_bar *base) nv50_bar_oneinit() argument
204 nv50_bar_dtor(struct nvkm_bar *base) nv50_bar_dtor() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/bar/ |
| H A D | nv50.c | 32 nv50_bar_flush(struct nvkm_bar *base) in nv50_bar_flush() argument
34 struct nv50_bar *bar = nv50_bar(base); in nv50_bar_flush()
35 struct nvkm_device *device = bar->base.subdev.device; in nv50_bar_flush()
37 spin_lock_irqsave(&bar->base.lock, flags); in nv50_bar_flush()
43 spin_unlock_irqrestore(&bar->base.lock, flags); in nv50_bar_flush()
47 nv50_bar_bar1_vmm(struct nvkm_bar *base) in nv50_bar_bar1_vmm() argument
49 return nv50_bar(base)->bar1_vmm; in nv50_bar_bar1_vmm()
53 nv50_bar_bar1_wait(struct nvkm_bar *base) in nv50_bar_bar1_wait() argument
55 nvkm_bar_flush(base); in nv50_bar_bar1_wait()
65 nv50_bar_bar1_init(struct nvkm_bar *base) in nv50_bar_bar1_init() argument
73 nv50_bar_bar2_vmm(struct nvkm_bar *base) nv50_bar_bar2_vmm() argument
85 nv50_bar_bar2_init(struct nvkm_bar *base) nv50_bar_bar2_init() argument
95 nv50_bar_init(struct nvkm_bar *base) nv50_bar_init() argument
106 nv50_bar_oneinit(struct nvkm_bar *base) nv50_bar_oneinit() argument
204 nv50_bar_dtor(struct nvkm_bar *base) nv50_bar_dtor() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| H A D | anx9805.c | 24 #define anx9805_pad(p) container_of((p), struct anx9805_pad, base)
25 #define anx9805_bus(p) container_of((p), struct anx9805_bus, base)
26 #define anx9805_aux(p) container_of((p), struct anx9805_aux, base)
31 struct nvkm_i2c_pad base; member
37 struct nvkm_i2c_bus base; member
43 anx9805_bus_xfer(struct nvkm_i2c_bus *base, struct i2c_msg *msgs, int num) in anx9805_bus_xfer() argument
45 struct anx9805_bus *bus = anx9805_bus(base); in anx9805_bus_xfer()
103 anx9805_bus_new(struct nvkm_i2c_pad *base, int id, u8 drive, in anx9805_bus_new() argument
106 struct anx9805_pad *pad = anx9805_pad(base); in anx9805_bus_new()
112 *pbus = &bus->base; in anx9805_bus_new()
130 struct nvkm_i2c_aux base; global() member
136 anx9805_aux_xfer(struct nvkm_i2c_aux *base, bool retry, u8 type, u32 addr, u8 *data, u8 *size) anx9805_aux_xfer() argument
192 anx9805_aux_lnk_ctl(struct nvkm_i2c_aux *base, int link_nr, int link_bw, bool enh) anx9805_aux_lnk_ctl() argument
232 anx9805_aux_new(struct nvkm_i2c_pad *base, int id, u8 drive, struct nvkm_i2c_aux **pbus) anx9805_aux_new() argument
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/ |
| H A D | nv50.c | 24 #define nv50_instmem(p) container_of((p), struct nv50_instmem, base)
33 struct nvkm_instmem base; member
43 #define nv50_instobj(p) container_of((p), struct nv50_instobj, base.memory)
46 struct nvkm_instobj base; member
60 struct nvkm_device *device = imem->base.subdev.device; in nv50_instobj_wr32_slow()
61 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; in nv50_instobj_wr32_slow() local
65 spin_lock_irqsave(&imem->base.lock, flags); in nv50_instobj_wr32_slow()
66 if (unlikely(imem->addr != base)) { in nv50_instobj_wr32_slow()
67 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_wr32_slow()
68 imem->addr = base; in nv50_instobj_wr32_slow()
80 u64 base = (nvkm_memory_addr(iobj->ram) + offset) & 0xffffff00000ULL; nv50_instobj_rd32_slow() local
356 nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, struct nvkm_memory **pmemory) nv50_instobj_new() argument
381 nv50_instmem_fini(struct nvkm_instmem *base) nv50_instmem_fini() argument
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
| H A D | dpu_5_0_sm8150.h | 26 .base = 0x0, .len = 0x45c,
44 .base = 0x1000, .len = 0x1e0,
49 .base = 0x1200, .len = 0x1e0,
54 .base = 0x1400, .len = 0x1e0,
59 .base = 0x1600, .len = 0x1e0,
64 .base = 0x1800, .len = 0x1e0,
69 .base = 0x1a00, .len = 0x1e0,
78 .base = 0x4000, .len = 0x1f0,
86 .base = 0x6000, .len = 0x1f0,
94 .base
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/ |
| H A D | vmwgfx_fence.c | 54 struct ttm_base_object base; member
87 return container_of(fence->base.lock, struct vmw_fence_manager, lock); in fman_from_fence()
115 container_of(f, struct vmw_fence_obj, base); in vmw_fence_obj_destroy()
139 container_of(f, struct vmw_fence_obj, base); in vmw_fence_enable_signaling()
146 if (seqno - fence->base.seqno < VMW_FENCE_WRAP) in vmw_fence_enable_signaling()
155 struct dma_fence_cb base; member
163 container_of(cb, struct vmwgfx_wait_cb, base); in vmwgfx_wait_cb()
173 container_of(f, struct vmw_fence_obj, base); in vmw_fence_wait()
196 cb.base.func = vmwgfx_wait_cb; in vmw_fence_wait()
198 list_add(&cb.base in vmw_fence_wait()
591 struct ttm_base_object *base = *p_base; vmw_user_fence_base_release() local
781 struct ttm_base_object *base = ttm_base_object_lookup(tfile, handle); vmw_fence_obj_lookup() local
806 struct ttm_base_object *base; vmw_fence_obj_wait_ioctl() local
860 struct ttm_base_object *base; vmw_fence_obj_signaled_ioctl() local
1046 struct drm_pending_event base; global() member
1124 struct ttm_base_object *base = vmw_fence_event_ioctl() local
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_resource.c | 134 /* compile time expand base address. */
446 return &opp->base; in dce120_opp_create()
465 return &aux_engine->base; in dce120_aux_engine_create()
555 clk_src->base.dp_clk_src = dp_clk_src; in dce120_clock_source_create()
556 return &clk_src->base; in dce120_clock_source_create()
595 return &tg110->base; in dce120_timing_generator_create()
608 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
609 if (pool->base.opps[i] != NULL) in dce120_resource_destruct()
610 dce110_opp_destroy(&pool->base.opps[i]); in dce120_resource_destruct()
612 if (pool->base in dce120_resource_destruct()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce120/ |
| H A D | dce120_resource.c | 132 /* compile time expand base address. */
437 return &opp->base; in dce120_opp_create()
456 return &aux_engine->base; in dce120_aux_engine_create()
547 clk_src->base.dp_clk_src = dp_clk_src; in dce120_clock_source_create()
548 return &clk_src->base; in dce120_clock_source_create()
587 return &tg110->base; in dce120_timing_generator_create()
600 for (i = 0; i < pool->base.pipe_count; i++) { in dce120_resource_destruct()
601 if (pool->base.opps[i] != NULL) in dce120_resource_destruct()
602 dce110_opp_destroy(&pool->base.opps[i]); in dce120_resource_destruct()
604 if (pool->base in dce120_resource_destruct()
[all...] |
| /kernel/linux/linux-5.10/drivers/ide/ |
| H A D | tx4939ide.c | 84 static u16 tx4939ide_readw(void __iomem *base, u32 reg) in tx4939ide_readw() argument
86 return __raw_readw(base + tx4939ide_swizzlew(reg)); in tx4939ide_readw()
88 static u8 tx4939ide_readb(void __iomem *base, u32 reg) in tx4939ide_readb() argument
90 return __raw_readb(base + tx4939ide_swizzleb(reg)); in tx4939ide_readb()
92 static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg) in tx4939ide_writel() argument
94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); in tx4939ide_writel()
96 static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg) in tx4939ide_writew() argument
98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); in tx4939ide_writew()
100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) in tx4939ide_writeb() argument
102 __raw_writeb(val, base in tx4939ide_writeb()
151 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_check_error_ints() local
176 void __iomem *base; tx4939ide_clear_irq() local
193 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_cable_detect() local
204 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_host_set() local
218 tx4939ide_clear_dma_status(void __iomem *base) tx4939ide_clear_dma_status() argument
290 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_setup() local
318 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_end() local
345 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_test_irq() local
384 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_dma_sff_read_status() local
394 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_init_hwif() local
423 void __iomem *base = TX4939IDE_BASE(hwif); tx4939ide_tf_load_fixup() local
[all...] |
| /kernel/linux/linux-6.6/drivers/clk/stm32/ |
| H A D | clk-stm32-core.c | 24 void __iomem *base) in stm32_rcc_clock_init()
50 data->check_security(base, cfg_clock)) in stm32_rcc_clock_init()
54 hw = (*cfg_clock->func)(dev, data, base, &rlock, in stm32_rcc_clock_init()
71 void __iomem *base) in stm32_rcc_init()
83 err = stm32_rcc_reset_init(dev, match, base); in stm32_rcc_init()
90 err = stm32_rcc_clock_init(dev, match, base); in stm32_rcc_init()
99 static u8 stm32_mux_get_parent(void __iomem *base, in stm32_mux_get_parent() argument
107 val = readl(base + mux->offset) >> mux->shift; in stm32_mux_get_parent()
113 static int stm32_mux_set_parent(void __iomem *base, in stm32_mux_set_parent() argument
120 u32 reg = readl(base in stm32_mux_set_parent()
22 stm32_rcc_clock_init(struct device *dev, const struct of_device_id *match, void __iomem *base) stm32_rcc_clock_init() argument
70 stm32_rcc_init(struct device *dev, const struct of_device_id *match_data, void __iomem *base) stm32_rcc_init() argument
131 stm32_gate_endisable(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id, int enable) stm32_gate_endisable() argument
157 stm32_gate_disable_unused(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id) stm32_gate_disable_unused() argument
173 stm32_gate_is_enabled(void __iomem *base, struct clk_stm32_clock_data *data, u16 gate_id) stm32_gate_is_enabled() argument
205 stm32_divider_get_rate(void __iomem *base, struct clk_stm32_clock_data *data, u16 div_id, unsigned long parent_rate) stm32_divider_get_rate() argument
228 stm32_divider_set_rate(void __iomem *base, struct clk_stm32_clock_data *data, u16 div_id, unsigned long rate, unsigned long parent_rate) stm32_divider_set_rate() argument
624 clk_stm32_mux_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_mux_register() argument
645 clk_stm32_gate_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_gate_register() argument
666 clk_stm32_div_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_div_register() argument
687 clk_stm32_composite_register(struct device *dev, const struct stm32_rcc_match_data *data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) clk_stm32_composite_register() argument
[all...] |