Lines Matching refs:base
122 * @base: pointer to register struct
136 void __iomem *base;
156 int_en = readl(idev->base + MST_INT_ENABLE);
157 writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
164 int_en = readl(idev->base + MST_INT_ENABLE);
165 writel(int_en | mask, idev->base + MST_INT_ENABLE);
190 writel(0x01, idev->base + SOFT_RESET);
192 while (readl(idev->base + SOFT_RESET) & 1) {
200 writel(0x1, idev->base + GLOBAL_CONTROL);
215 writel(t_high, idev->base + SCL_HIGH_PERIOD);
217 writel(t_low, idev->base + SCL_LOW_PERIOD);
219 writel(t_setup, idev->base + SDA_SETUP_TIME);
221 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
223 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
238 writel(prescale, idev->base + TIMER_CLOCK_DIV);
240 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
246 writel(0x01, idev->base + INTERRUPT_ENABLE);
273 size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
277 int c = readl(idev->base + MST_DATA);
290 writel(msg->len, idev->base + MST_RX_XFER);
305 size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
310 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
317 u32 fifo_status = readl(idev->base + SLV_RX_FIFO);
327 val = readl(idev->base + SLV_DATA);
331 readl(idev->base + SLV_DATA); /* dummy read */
335 readl(idev->base + SLV_DATA); /* dummy read */
340 u32 status = readl(idev->base + SLV_INT_STATUS);
349 writel(val, idev->base + SLV_DATA);
353 writel(val, idev->base + SLV_DATA);
358 writel(INT_SLV, idev->base + INTERRUPT_STATUS);
368 status = readl(idev->base + INTERRUPT_STATUS);
376 status = readl(idev->base + MST_INT_STATUS);
405 readl(idev->base + MST_RX_BYTES_XFRD),
406 readl(idev->base + MST_RX_XFER),
407 readl(idev->base + MST_TX_BYTES_XFRD),
408 readl(idev->base + MST_TX_XFER));
431 writel(INT_MST, idev->base + INTERRUPT_STATUS);
458 writel(addr_1, idev->base + MST_ADDR_1);
459 writel(addr_2, idev->base + MST_ADDR_2);
471 if ((readl(idev->base + MST_COMMAND) & CMD_BUSY) == 0)
487 writel(msgs[0].len, idev->base + MST_TX_XFER);
488 writel(rlen, idev->base + MST_RX_XFER);
497 writel(CMD_SEQUENCE, idev->base + MST_COMMAND);
508 } else if (readl(idev->base + MST_COMMAND) & CMD_BUSY) {
551 writel(rx_xfer, idev->base + MST_RX_XFER);
552 writel(tx_xfer, idev->base + MST_TX_XFER);
559 wt_value = WT_VALUE(readl(idev->base + WAIT_TIMER_CONTROL));
561 writel(wt_value, idev->base + WAIT_TIMER_CONTROL);
567 writel(CMD_MANUAL, idev->base + MST_COMMAND);
570 writel(CMD_AUTO, idev->base + MST_COMMAND);
574 writel(WT_EN | wt_value, idev->base + WAIT_TIMER_CONTROL);
583 if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
638 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
647 tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
650 writel(tmp, idev->base + I2C_BUS_MONITOR);
657 return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
686 writel(GLOBAL_MST_EN | GLOBAL_SLV_EN, idev->base + GLOBAL_CONTROL);
687 writel(INT_MST | INT_SLV, idev->base + INTERRUPT_ENABLE);
694 writel(SLV_RX_ACSA1, idev->base + SLV_RX_CTL);
695 writel(dec_ctl, idev->base + SLV_ADDR_DEC_CTL);
696 writel(slave->addr, idev->base + SLV_ADDR_1);
701 writel(slv_int_mask, idev->base + SLV_INT_ENABLE);
711 writel(GLOBAL_MST_EN, idev->base + GLOBAL_CONTROL);
712 writel(INT_MST, idev->base + INTERRUPT_ENABLE);
737 void __iomem *base;
744 base = devm_platform_ioremap_resource(pdev, 0);
745 if (IS_ERR(base))
746 return PTR_ERR(base);
758 idev->base = base;