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/kernel/linux/linux-6.6/drivers/input/keyboard/
H A Dbcm-keypad.c67 void __iomem *base; member
102 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
104 state = readl(kp->base + KPSSRN_OFFSET(reg_num)); in bcm_kp_report_keys()
143 writel(kp->kpior, kp->base + KPIOR_OFFSET); in bcm_kp_start()
145 writel(kp->imr0_val, kp->base + KPIMR0_OFFSET); in bcm_kp_start()
146 writel(kp->imr1_val, kp->base + KPIMR1_OFFSET); in bcm_kp_start()
148 writel(kp->kpemr, kp->base + KPEMR0_OFFSET); in bcm_kp_start()
149 writel(kp->kpemr, kp->base + KPEMR1_OFFSET); in bcm_kp_start()
150 writel(kp->kpemr, kp->base + KPEMR2_OFFSET); in bcm_kp_start()
151 writel(kp->kpemr, kp->base in bcm_kp_start()
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/kernel/linux/linux-6.6/tools/testing/selftests/powerpc/
H A Dutils.c213 int base, intmax_t min, intmax_t max) in parse_bounded_int()
219 *result = strtoimax(buffer, &end, base); in parse_bounded_int()
237 int base, uintmax_t max) in parse_bounded_uint()
243 *result = strtoumax(buffer, &end, base); in parse_bounded_uint()
260 int parse_intmax(const char *buffer, size_t count, intmax_t *result, int base) in parse_intmax() argument
262 return parse_bounded_int(buffer, count, result, base, INTMAX_MIN, INTMAX_MAX); in parse_intmax()
265 int parse_uintmax(const char *buffer, size_t count, uintmax_t *result, int base) in parse_uintmax() argument
267 return parse_bounded_uint(buffer, count, result, base, UINTMAX_MAX); in parse_uintmax()
270 int parse_int(const char *buffer, size_t count, int *result, int base) in parse_int() argument
273 int err = parse_bounded_int(buffer, count, &parsed, base, INT_MI in parse_int()
212 parse_bounded_int(const char *buffer, size_t count, intmax_t *result, int base, intmax_t min, intmax_t max) parse_bounded_int() argument
236 parse_bounded_uint(const char *buffer, size_t count, uintmax_t *result, int base, uintmax_t max) parse_bounded_uint() argument
279 parse_uint(const char *buffer, size_t count, unsigned int *result, int base) parse_uint() argument
288 parse_long(const char *buffer, size_t count, long *result, int base) parse_long() argument
297 parse_ulong(const char *buffer, size_t count, unsigned long *result, int base) parse_ulong() argument
306 read_long(const char *path, long *result, int base) read_long() argument
318 read_ulong(const char *path, unsigned long *result, int base) read_ulong() argument
330 write_long(const char *path, long result, int base) write_long() argument
355 write_ulong(const char *path, unsigned long result, int base) write_ulong() argument
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/kernel/linux/linux-6.6/mm/
H A Dcma.c67 * Find the offset of the base PFN from the specified align_order.
164 * @base: Base address of the reserved area
174 int __init cma_init_reserved_mem(phys_addr_t base, phys_addr_t size, in cma_init_reserved_mem() argument
187 if (!size || !memblock_is_region_reserved(base, size)) in cma_init_reserved_mem()
195 if (!IS_ALIGNED(base | size, CMA_MIN_ALIGNMENT_BYTES)) in cma_init_reserved_mem()
209 cma->base_pfn = PFN_DOWN(base); in cma_init_reserved_mem()
221 * @base: Base address of the reserved area optional, use 0 for any
236 * If @fixed is true, reserve contiguous area at exactly @base. If false,
237 * reserve in range from @base to @limit.
239 int __init cma_declare_contiguous_nid(phys_addr_t base, in cma_declare_contiguous_nid() argument
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/third_party/mesa3d/src/gallium/auxiliary/vl/
H A Dvl_winsys_dri.c59 struct vl_screen base; member
254 tex = scrn->base.pscreen->resource_from_handle(scrn->base.pscreen, &templ, in vl_dri2_screen_texture_from_drawable()
416 scrn->base.xcb_screen = get_xcb_screen(s, screen); in vl_dri2_screen_create()
417 if (!scrn->base.xcb_screen) in vl_dri2_screen_create()
434 scrn->conn, ((xcb_screen_t *)(scrn->base.xcb_screen))->root, driverType); in vl_dri2_screen_create()
455 scrn->conn, ((xcb_screen_t *)(scrn->base.xcb_screen))->root, magic); in vl_dri2_screen_create()
461 if (pipe_loader_drm_probe_fd(&scrn->base.dev, fd)) in vl_dri2_screen_create()
462 scrn->base.pscreen = pipe_loader_create_screen(scrn->base in vl_dri2_screen_create()
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/third_party/gn/src/gn/
H A Dxcode_writer.cc17 #include "base/environment.h"
18 #include "base/files/file_enumerator.h"
19 #include "base/logging.h"
20 #include "base/sha1.h"
21 #include "base/stl_util.h"
22 #include "base/strings/string_number_conversions.h"
23 #include "base/strings/string_split.h"
24 #include "base/strings/string_util.h"
87 base::Environment* environment) { in GetBuildScript()
124 base in GetBuildScript()
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/third_party/mesa3d/src/gallium/drivers/nouveau/nv50/
H A Dnv50_state_validate.c22 struct nouveau_pushbuf *push = nv50->base.pushbuf; in nv50_validate_fb()
48 bo = mt->base.bo; in nv50_validate_fb()
58 PUSH_DATAh(push, mt->base.address + sf->offset); in nv50_validate_fb()
59 PUSH_DATA (push, mt->base.address + sf->offset); in nv50_validate_fb()
60 PUSH_DATA (push, nv50_format_table[sf->base.format].rt); in nv50_validate_fb()
62 assert(sf->base.texture->target != PIPE_BUFFER); in nv50_validate_fb()
64 PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); in nv50_validate_fb()
87 if (mt->base.status & NOUVEAU_BUFFER_STATUS_GPU_READING) in nv50_validate_fb()
89 mt->base.status |= NOUVEAU_BUFFER_STATUS_GPU_WRITING; in nv50_validate_fb()
90 mt->base in nv50_validate_fb()
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/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-ixp4xx.c50 * @base: remapped I/O-memory base
58 void __iomem *base; member
67 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
134 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
136 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
138 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_set_type()
141 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
143 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
146 val = __raw_readl(g->base in ixp4xx_gpio_irq_set_type()
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H A Dgpio-104-idi-48.c27 static unsigned int base[MAX_NUM_IDI_48]; variable
29 module_param_hw_array(base, uint, ioport, &num_idi_48, 0);
30 MODULE_PARM_DESC(base, "ACCES 104-IDI-48 base addresses");
42 * @base: base port address of the GPIO device
50 unsigned base; member
77 return !!(inb(idi48gpio->base + base_offset) & mask); in idi_48_gpio_get()
98 port_addr = idi48gpio->base + ports[offset / 8]; in idi_48_gpio_get_multiple()
133 outb(idi48gpio->cos_enb, idi48gpio->base in idi_48_irq_mask()
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/kernel/linux/linux-5.10/drivers/clocksource/
H A Dtimer-fsl-ftm.c48 static inline void ftm_counter_enable(void __iomem *base) in ftm_counter_enable() argument
53 val = ftm_readl(base + FTM_SC); in ftm_counter_enable()
56 ftm_writel(val, base + FTM_SC); in ftm_counter_enable()
59 static inline void ftm_counter_disable(void __iomem *base) in ftm_counter_disable() argument
64 val = ftm_readl(base + FTM_SC); in ftm_counter_disable()
66 ftm_writel(val, base + FTM_SC); in ftm_counter_disable()
69 static inline void ftm_irq_acknowledge(void __iomem *base) in ftm_irq_acknowledge() argument
73 val = ftm_readl(base + FTM_SC); in ftm_irq_acknowledge()
75 ftm_writel(val, base + FTM_SC); in ftm_irq_acknowledge()
78 static inline void ftm_irq_enable(void __iomem *base) in ftm_irq_enable() argument
87 ftm_irq_disable(void __iomem *base) ftm_irq_disable() argument
96 ftm_reset_counter(void __iomem *base) ftm_reset_counter() argument
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/kernel/linux/linux-5.10/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); in alchemy_gpio1_input_enable() local
276 __raw_writel(0, base + 0x110); /* the write op is key */ in alchemy_gpio1_input_enable()
286 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in __alchemy_gpio2_mod_dir() local
288 unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); in __alchemy_gpio2_mod_dir()
294 __raw_writel(d, base + AU1000_GPIO2_DIR); in __alchemy_gpio2_mod_dir()
300 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_set_value() local
303 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); in alchemy_gpio2_set_value()
309 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_get_value() local
310 return __raw_readl(base + AU1000_GPIO2_PINSTATE) & in alchemy_gpio2_get_value()
361 void __iomem *base in __alchemy_gpio2_mod_int() local
443 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); alchemy_gpio2_enable() local
457 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); alchemy_gpio2_disable() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c37 dwbc20->base.ctx
40 dwbc20->base.ctx->logger
64 DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps()
67 DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps()
75 DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); in dwb2_config_dwb_cnv()
107 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_enable()
110 DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst); in dwb2_enable()
138 DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst); in dwb2_disable()
166 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_update()
169 DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base in dwb2_update()
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/kernel/linux/linux-6.6/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h275 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1000_SYS_PHYS_ADDR); in alchemy_gpio1_input_enable() local
276 __raw_writel(0, base + 0x110); /* the write op is key */ in alchemy_gpio1_input_enable()
286 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in __alchemy_gpio2_mod_dir() local
288 unsigned long d = __raw_readl(base + AU1000_GPIO2_DIR); in __alchemy_gpio2_mod_dir()
294 __raw_writel(d, base + AU1000_GPIO2_DIR); in __alchemy_gpio2_mod_dir()
300 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_set_value() local
303 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); in alchemy_gpio2_set_value()
309 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); in alchemy_gpio2_get_value() local
310 return __raw_readl(base + AU1000_GPIO2_PINSTATE) & in alchemy_gpio2_get_value()
361 void __iomem *base in __alchemy_gpio2_mod_int() local
443 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); alchemy_gpio2_enable() local
457 void __iomem *base = (void __iomem *)KSEG1ADDR(AU1500_GPIO2_PHYS_ADDR); alchemy_gpio2_disable() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_kms.c108 if (!last || (new->base.zpos > last->base.zpos)) { in komeda_plane_state_list_add()
115 if (new->base.zpos < node->base.zpos) { in komeda_plane_state_list_add()
118 } else if (node->base.zpos == new->base.zpos) { in komeda_plane_state_list_add()
119 struct drm_plane *a = node->base.plane; in komeda_plane_state_list_add()
120 struct drm_plane *b = new->base.plane; in komeda_plane_state_list_add()
126 a->name, b->name, node->base.zpos); in komeda_plane_state_list_add()
147 crtc->base in komeda_crtc_normalize_zpos()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/dispnv04/
H A Ddisp.c117 nv_crtc->save(&nv_crtc->base); in nv04_display_init()
120 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) in nv04_display_init()
121 encoder->enc_save(&encoder->base.base); in nv04_display_init()
197 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) in nv04_display_destroy()
198 encoder->enc_restore(&encoder->base.base); in nv04_display_destroy()
200 list_for_each_entry(nv_crtc, &dev->mode_config.crtc_list, base in nv04_display_destroy()
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/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dgf119.c38 struct nvkm_subdev *subdev = &disp->base.engine.subdev; in gf119_disp_super()
44 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
52 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
59 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
64 nvkm_outp_route(&disp->base); in gf119_disp_super()
65 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
70 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
77 list_for_each_entry(head, &disp->base.head, head) { in gf119_disp_super()
84 list_for_each_entry(head, &disp->base.head, head) in gf119_disp_super()
92 struct nvkm_subdev *subdev = &disp->base in gf119_disp_intr_error()
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/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-vt8500.c52 void __iomem *base; member
64 while ((readl(vt8500->base + REG_STATUS) & mask) && --loops) in pwm_busy_wait()
108 writel(prescale, vt8500->base + REG_SCALAR(pwm->hwpwm)); in vt8500_pwm_config()
111 writel(pv, vt8500->base + REG_PERIOD(pwm->hwpwm)); in vt8500_pwm_config()
114 writel(dc, vt8500->base + REG_DUTY(pwm->hwpwm)); in vt8500_pwm_config()
117 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
119 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_config()
138 val = readl(vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
140 writel(val, vt8500->base + REG_CTRL(pwm->hwpwm)); in vt8500_pwm_enable()
151 val = readl(vt8500->base in vt8500_pwm_disable()
[all...]
/kernel/linux/linux-5.10/drivers/media/rc/
H A Dsunxi-cir.c95 void __iomem *base; member
114 status = readl(ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
117 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); in sunxi_ir_irq()
127 dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); in sunxi_ir_irq()
202 dev_err(dev, "set ir base clock failed!\n"); in sunxi_ir_probe()
205 dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); in sunxi_ir_probe()
221 ir->base = devm_ioremap_resource(dev, res); in sunxi_ir_probe()
222 if (IS_ERR(ir->base)) { in sunxi_ir_probe()
223 ret = PTR_ERR(ir->base); in sunxi_ir_probe()
272 writel(REG_CTL_MD, ir->base in sunxi_ir_probe()
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/kernel/linux/linux-5.10/drivers/parport/
H A Dparport_sunbpp.c53 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_disable_irq()
63 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_enable_irq()
73 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_write_data()
81 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_read_data()
88 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in status_sunbpp_to_pc()
111 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in control_sunbpp_to_pc()
139 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_frob_control()
198 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_forward()
208 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_reverse()
275 void __iomem *base; in bpp_probe() local
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/kernel/linux/linux-6.6/drivers/watchdog/
H A Drealtek_otto_wdt.c69 void __iomem *base; member
79 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
81 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_start()
91 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
93 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_stop()
102 iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR); in otto_wdt_ping()
151 v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_determine_timeouts()
158 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_determine_timeouts()
202 iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL); in otto_wdt_restart()
213 iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base in otto_wdt_phase1_isr()
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/kernel/linux/linux-6.6/drivers/soc/qcom/
H A Dice.c38 writel((val), (engine)->base + (reg))
41 readl((engine)->base + (reg))
45 void __iomem *base; member
122 err = readl_poll_timeout(ice->base + QCOM_ICE_REG_BIST_STATUS, in qcom_ice_wait_bist_status()
209 void __iomem *base) in qcom_ice_create()
226 engine->base = base; in qcom_ice_create()
270 void __iomem *base; in of_qcom_ice_get() local
282 base = devm_ioremap_resource(&pdev->dev, res); in of_qcom_ice_get()
283 if (IS_ERR(base)) in of_qcom_ice_get()
208 qcom_ice_create(struct device *dev, void __iomem *base) qcom_ice_create() argument
334 void __iomem *base; qcom_ice_probe() local
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/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-en7523.c46 void __iomem *base; member
153 static unsigned int en7523_get_base_rate(void __iomem *base, unsigned int i) in en7523_get_base_rate() argument
161 val = readl(base + desc->base_reg); in en7523_get_base_rate()
171 static u32 en7523_get_div(void __iomem *base, int i) in en7523_get_div() argument
180 val = readl(base + reg); in en7523_get_div()
194 return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1); in en7523_pci_is_enabled()
200 void __iomem *np_base = cg->base; in en7523_pci_prepare()
239 void __iomem *np_base = cg->base; in en7523_pci_unprepare()
265 cg->base = np_base; in en7523_register_pcie_clk()
276 void __iomem *base, voi in en7523_register_clocks()
275 en7523_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data, void __iomem *base, void __iomem *np_base) en7523_register_clocks() argument
308 void __iomem *base, *np_base; en7523_clk_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-ixp4xx.c46 * @base: remapped I/O-memory base
54 void __iomem *base; member
63 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
139 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
141 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
143 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_set_type()
146 val = __raw_readl(g->base + int_reg); in ixp4xx_gpio_irq_set_type()
148 __raw_writel(val, g->base + int_reg); in ixp4xx_gpio_irq_set_type()
151 val = __raw_readl(g->base in ixp4xx_gpio_irq_set_type()
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c37 dwbc20->base.ctx
40 dwbc20->base.ctx->logger
64 DC_LOG_DWB("%s SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps()
67 DC_LOG_DWB("%s NOT SUPPORTED! inst = %d", __func__, dwbc20->base.inst); in dwb2_get_caps()
75 DC_LOG_DWB("%s inst = %d", __func__, dwbc20->base.inst); in dwb2_config_dwb_cnv()
107 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_enable()
110 DC_LOG_DWB("%s inst = %d, ENABLED", __func__, dwbc20->base.inst); in dwb2_enable()
138 DC_LOG_DWB("%s inst = %d, Disabled", __func__, dwbc20->base.inst); in dwb2_disable()
166 DC_LOG_DWB("%s inst = %d, FAILED!LUMA SCALING NOT SUPPORTED", __func__, dwbc20->base.inst); in dwb2_update()
169 DC_LOG_DWB("%s inst = %d, scaling", __func__, dwbc20->base in dwb2_update()
[all...]
/kernel/linux/linux-6.6/drivers/clocksource/
H A Dtimer-fsl-ftm.c48 static inline void ftm_counter_enable(void __iomem *base) in ftm_counter_enable() argument
53 val = ftm_readl(base + FTM_SC); in ftm_counter_enable()
56 ftm_writel(val, base + FTM_SC); in ftm_counter_enable()
59 static inline void ftm_counter_disable(void __iomem *base) in ftm_counter_disable() argument
64 val = ftm_readl(base + FTM_SC); in ftm_counter_disable()
66 ftm_writel(val, base + FTM_SC); in ftm_counter_disable()
69 static inline void ftm_irq_acknowledge(void __iomem *base) in ftm_irq_acknowledge() argument
73 val = ftm_readl(base + FTM_SC); in ftm_irq_acknowledge()
75 ftm_writel(val, base + FTM_SC); in ftm_irq_acknowledge()
78 static inline void ftm_irq_enable(void __iomem *base) in ftm_irq_enable() argument
87 ftm_irq_disable(void __iomem *base) ftm_irq_disable() argument
96 ftm_reset_counter(void __iomem *base) ftm_reset_counter() argument
[all...]
/kernel/linux/linux-6.6/drivers/parport/
H A Dparport_sunbpp.c53 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_disable_irq()
63 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_enable_irq()
73 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_write_data()
81 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_read_data()
88 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in status_sunbpp_to_pc()
111 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in control_sunbpp_to_pc()
139 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_frob_control()
198 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_forward()
208 struct bpp_regs __iomem *regs = (struct bpp_regs __iomem *)p->base; in parport_sunbpp_data_reverse()
275 void __iomem *base; in bpp_probe() local
[all...]

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