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/third_party/gn/src/gn/
H A Dninja_tools.h10 #include "base/files/file_path.h"
25 bool InvokeNinjaRestatTool(const base::FilePath& ninja_executable,
26 const base::FilePath& build_dir,
27 const std::vector<base::FilePath>& files_to_restat,
33 bool InvokeNinjaCleanDeadTool(const base::FilePath& ninja_executable,
34 const base::FilePath& build_dir,
40 bool InvokeNinjaRecompactTool(const base::FilePath& ninja_executable,
41 const base::FilePath& build_dir,
/third_party/typescript/tests/baselines/reference/
H A DmoduleResolutionWithSuffixes_one_externalModule.js13 function base() {} function
14 exports.base = base;
16 export declare function base(): void;
30 function base() { }
31 exports.base = base;
H A DmoduleResolutionWithSuffixes_one_externalModule_withPaths.js13 function base() {} function
14 exports.base = base;
16 export declare function base(): void;
32 function base() { }
33 exports.base = base;
/kernel/linux/linux-5.10/drivers/watchdog/
H A Daspeed_wdt.c18 void __iomem *base; member
108 writel(0, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
109 writel(count, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_enable()
110 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_enable()
111 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_enable()
128 writel(wdt->ctrl, wdt->base + WDT_CTRL); in aspeed_wdt_stop()
137 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_ping()
152 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE); in aspeed_wdt_set_timeout()
153 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART); in aspeed_wdt_set_timeout()
176 u32 status = readl(wdt->base in access_cs0_show()
[all...]
/kernel/linux/linux-5.10/drivers/pwm/
H A Dpwm-bcm-kona.c70 void __iomem *base; member
85 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
89 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_prepare_for_settings()
100 unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
105 writel(value, kp->base + PWM_CONTROL_OFFSET); in kona_pwmc_apply_settings()
161 value = readl(kp->base + PRESCALE_OFFSET); in kona_pwmc_config()
164 writel(value, kp->base + PRESCALE_OFFSET); in kona_pwmc_config()
166 writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan)); in kona_pwmc_config()
168 writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); in kona_pwmc_config()
192 value = readl(kp->base in kona_pwmc_set_polarity()
[all...]
H A Dpwm-hibvt.c38 void __iomem *base; member
71 static void hibvt_pwm_set_bits(void __iomem *base, u32 offset, in hibvt_pwm_set_bits() argument
74 void __iomem *address = base + offset; in hibvt_pwm_set_bits()
87 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
95 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
110 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG0_ADDR(pwm->hwpwm), in hibvt_pwm_config()
113 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CFG1_ADDR(pwm->hwpwm), in hibvt_pwm_config()
124 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
127 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_set_polarity()
135 void __iomem *base; in hibvt_pwm_get_state() local
[all...]
/kernel/linux/linux-5.10/drivers/pci/controller/dwc/
H A Dpcie-uniphier-ep.c58 void __iomem *base; member
73 val = readl(priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
78 writel(val, priv->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
86 val = readl(priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
91 writel(val, priv->base + PCL_RSTCTRL2); in uniphier_pcie_phy_reset()
99 val = readl(priv->base + PCL_MODE); in uniphier_pcie_init_ep()
101 writel(val, priv->base + PCL_MODE); in uniphier_pcie_init_ep()
104 val = readl(priv->base + PCL_APP_CLK_CTRL); in uniphier_pcie_init_ep()
106 writel(val, priv->base + PCL_APP_CLK_CTRL); in uniphier_pcie_init_ep()
109 val = readl(priv->base in uniphier_pcie_init_ep()
[all...]
/kernel/linux/linux-5.10/drivers/rtc/
H A Drtc-88pm80x.c103 unsigned long ticks, base, data; in pm80x_rtc_read_time() local
105 base = ((unsigned long)buf[3] << 24) | (buf[2] << 16) | in pm80x_rtc_read_time()
113 ticks = base + data; in pm80x_rtc_read_time()
114 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm80x_rtc_read_time()
115 base, data, ticks); in pm80x_rtc_read_time()
124 unsigned long ticks, base, data; in pm80x_rtc_set_time() local
132 base = ticks - data; in pm80x_rtc_set_time()
133 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm80x_rtc_set_time()
134 base, data, ticks); in pm80x_rtc_set_time()
135 buf[0] = base in pm80x_rtc_set_time()
148 unsigned long ticks, base, data; pm80x_rtc_read_alarm() local
174 unsigned long ticks, base, data; pm80x_rtc_set_alarm() local
[all...]
/kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/
H A Dia_css_eed1_8.host.c94 unsigned int i, j, base; in ia_css_eed1_8_vmem_encode() local
172 base = shuffle_block * i; in ia_css_eed1_8_vmem_encode()
175 to->e_dew_enh_x[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
178 to->e_dew_enh_y[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
184 to->e_dew_enh_a[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
191 to->e_dew_enh_f[0][base + j] = (min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
200 to->e_dew_enh_a[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; in ia_css_eed1_8_vmem_encode()
201 to->e_dew_enh_f[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; in ia_css_eed1_8_vmem_encode()
204 to->chgrinv_x[0][base + j] = chgrinv_x[j]; in ia_css_eed1_8_vmem_encode()
205 to->chgrinv_a[0][base in ia_css_eed1_8_vmem_encode()
[all...]
/kernel/linux/linux-6.6/drivers/staging/media/atomisp/pci/isp/kernels/eed1_8/
H A Dia_css_eed1_8.host.c94 unsigned int i, j, base; in ia_css_eed1_8_vmem_encode() local
172 base = shuffle_block * i; in ia_css_eed1_8_vmem_encode()
175 to->e_dew_enh_x[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
178 to->e_dew_enh_y[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
184 to->e_dew_enh_a[0][base + j] = min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
191 to->e_dew_enh_f[0][base + j] = (min_t(int, max_t(int, in ia_css_eed1_8_vmem_encode()
200 to->e_dew_enh_a[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; in ia_css_eed1_8_vmem_encode()
201 to->e_dew_enh_f[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; in ia_css_eed1_8_vmem_encode()
204 to->chgrinv_x[0][base + j] = chgrinv_x[j]; in ia_css_eed1_8_vmem_encode()
205 to->chgrinv_a[0][base in ia_css_eed1_8_vmem_encode()
[all...]
/kernel/linux/linux-6.6/drivers/rtc/
H A Drtc-88pm80x.c103 unsigned long ticks, base, data; in pm80x_rtc_read_time() local
105 base = ((unsigned long)buf[3] << 24) | (buf[2] << 16) | in pm80x_rtc_read_time()
113 ticks = base + data; in pm80x_rtc_read_time()
114 dev_dbg(info->dev, "get base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm80x_rtc_read_time()
115 base, data, ticks); in pm80x_rtc_read_time()
124 unsigned long ticks, base, data; in pm80x_rtc_set_time() local
132 base = ticks - data; in pm80x_rtc_set_time()
133 dev_dbg(info->dev, "set base:0x%lx, RO count:0x%lx, ticks:0x%lx\n", in pm80x_rtc_set_time()
134 base, data, ticks); in pm80x_rtc_set_time()
135 buf[0] = base in pm80x_rtc_set_time()
148 unsigned long ticks, base, data; pm80x_rtc_read_alarm() local
174 unsigned long ticks, base, data; pm80x_rtc_set_alarm() local
[all...]
/kernel/linux/linux-6.6/drivers/pwm/
H A Dpwm-bcm-iproc.c38 void __iomem *base; member
51 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
53 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
63 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
65 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
78 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
97 value = readl(ip->base + IPROC_PWM_PRESCALE_OFFSET); in iproc_pwmc_get_state()
103 value = readl(ip->base + IPROC_PWM_PERIOD_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
107 value = readl(ip->base + IPROC_PWM_DUTY_CYCLE_OFFSET(pwm->hwpwm)); in iproc_pwmc_get_state()
158 value = readl(ip->base in iproc_pwmc_apply()
[all...]
/kernel/linux/linux-6.6/drivers/net/ethernet/litex/
H A Dlitex_liteeth.c41 void __iomem *base; member
65 rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT); in liteeth_rx()
66 len = litex_read32(priv->base + LITEETH_WRITER_LENGTH); in liteeth_rx()
98 reg = litex_read8(priv->base + LITEETH_READER_EV_PENDING); in liteeth_interrupt()
102 litex_write8(priv->base + LITEETH_READER_EV_PENDING, reg); in liteeth_interrupt()
105 reg = litex_read8(priv->base + LITEETH_WRITER_EV_PENDING); in liteeth_interrupt()
108 litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, reg); in liteeth_interrupt()
120 litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); in liteeth_open()
121 litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1); in liteeth_open()
130 litex_write8(priv->base in liteeth_open()
[all...]
/kernel/linux/linux-6.6/drivers/nvmem/
H A Drockchip-otp.c79 void __iomem *base; member
112 ret = readl_poll_timeout_atomic(otp->base + reg, status, in rockchip_otp_wait_status()
118 writel(flag, otp->base + reg); in rockchip_otp_wait_status()
128 otp->base + OTPC_SBPI_CTRL); in rockchip_otp_ecc_enable()
130 writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE); in rockchip_otp_ecc_enable()
132 otp->base + OTPC_SBPI_CMD0_OFFSET); in rockchip_otp_ecc_enable()
134 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in rockchip_otp_ecc_enable()
136 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET); in rockchip_otp_ecc_enable()
138 writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); in rockchip_otp_ecc_enable()
166 writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base in px30_otp_read()
[all...]
/kernel/linux/linux-6.6/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi-mt8173.c125 void __iomem *base = mipi_tx->regs; in mtk_mipi_tx_pll_prepare() local
155 mtk_phy_update_bits(base + MIPITX_DSI_BG_CON, in mtk_mipi_tx_pll_prepare()
168 mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON, in mtk_mipi_tx_pll_prepare()
173 mtk_phy_set_bits(base + MIPITX_DSI_CON, in mtk_mipi_tx_pll_prepare()
176 mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR, in mtk_mipi_tx_pll_prepare()
180 mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN); in mtk_mipi_tx_pll_prepare()
182 mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0, in mtk_mipi_tx_pll_prepare()
197 writel(pcw, base + MIPITX_DSI_PLL_CON2); in mtk_mipi_tx_pll_prepare()
199 mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN); in mtk_mipi_tx_pll_prepare()
201 mtk_phy_set_bits(base in mtk_mipi_tx_pll_prepare()
217 void __iomem *base = mipi_tx->regs; mtk_mipi_tx_pll_unprepare() local
[all...]
/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-ls2x.c66 void __iomem *base; member
79 if (!(readb(priv->base + I2C_LS2X_SR) & LS2X_SR_IF)) in ls2x_i2c_isr()
82 writeb(LS2X_CR_IACK, priv->base + I2C_LS2X_CR); in ls2x_i2c_isr()
109 priv->base + I2C_LS2X_PRER); in ls2x_i2c_adjust_bus_speed()
115 writeb(readb(priv->base + I2C_LS2X_CTR) & ~CTR_FREQ_MASK, in ls2x_i2c_init()
116 priv->base + I2C_LS2X_CTR); in ls2x_i2c_init()
121 writeb(readb(priv->base + I2C_LS2X_CTR) | CTR_READY_MASK, in ls2x_i2c_init()
122 priv->base + I2C_LS2X_CTR); in ls2x_i2c_init()
130 writeb(txdata, priv->base + I2C_LS2X_CR); in ls2x_i2c_xfer_byte()
137 rxdata = readb(priv->base in ls2x_i2c_xfer_byte()
[all...]
/third_party/mesa3d/src/gallium/drivers/virgl/
H A Dvirgl_transfer_queue.c58 switch (xfer->base.resource->target) { in transfer_dim()
113 if (xfer->hw_res != hw_res || xfer->base.level != level) in transfer_overlap()
122 box_min_max(&xfer->base.box, dim, &xfer_min, &xfer_max); in transfer_overlap()
158 return transfer_overlap(queued, current->hw_res, current->base.level, in transfers_intersect()
159 &current->base.box, true); in transfers_intersect()
175 u_box_union_2d(&current->base.box, &current->base.box, &queued->base.box); in replace_unmapped_transfer()
176 current->offset = current->base.box.x; in replace_unmapped_transfer()
188 &queued->base in transfer_put()
[all...]
/third_party/skia/third_party/externals/sfntly/java/src/com/google/typography/font/sfntly/table/opentype/component/
H A DOffsetRecordTable.java21 protected OffsetRecordTable(ReadableFontData data, int base, boolean dataIsCanonical) { in OffsetRecordTable() argument
22 super(data, base, dataIsCanonical); in OffsetRecordTable()
23 recordList = new NumRecordList(data.slice(base + headerSize())); in OffsetRecordTable()
31 super(records.readData, records.base, false); in OffsetRecordTable()
98 private final int base; field in OffsetRecordTable.Builder
104 base = 0; in Builder()
108 this(table.readFontData(), table.base, table.dataIsCanonical); in Builder()
115 protected Builder(ReadableFontData data, int base, boolean dataIsCanonical) { in Builder() argument
117 this.base = base; in Builder()
228 readTable(ReadableFontData data, int base, boolean dataIsCanonical) readTable() argument
247 initFromData(ReadableFontData data, int base) initFromData() argument
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_hdcp.c46 drm_modeset_lock(&mgr->base.lock, state->acquire_ctx); in intel_conn_to_vcpi()
47 mst_state = to_drm_dp_mst_topology_state(mgr->base.state); in intel_conn_to_vcpi()
123 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdcp_read_valid_bksv()
167 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdcp2_capable()
384 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdcp_validate_v_prime()
386 enum port port = dig_port->base.port; in intel_hdcp_validate_v_prime()
626 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdcp_auth_downstream()
709 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_hdcp_auth()
713 enum port port = dig_port->base in intel_hdcp_auth()
[all...]
H A Dintel_hdmi.c64 return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev); in intel_hdmi_to_i915()
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_write_infoframe()
312 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_read_infoframe()
327 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in ibx_infoframes_enabled()
349 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in cpt_write_infoframe()
390 struct drm_i915_private *dev_priv = to_i915(encoder->base in cpt_read_infoframe()
[all...]
/kernel/linux/linux-5.10/drivers/bus/
H A Dmvebu-mbus.c130 u32 base; member
201 int win, int *enabled, u64 *base, in mvebu_mbus_read_window()
216 *base = ((u64)basereg & WIN_BASE_HIGH) << 32; in mvebu_mbus_read_window()
217 *base |= (basereg & WIN_BASE_LOW); in mvebu_mbus_read_window()
268 * Checks whether the given (base, base+size) area doesn't overlap an
272 phys_addr_t base, size_t size, in mvebu_mbus_window_conflicts()
275 u64 end = (u64)base + size; in mvebu_mbus_window_conflicts()
297 if ((u64)base < wend && end > wbase) in mvebu_mbus_window_conflicts()
305 phys_addr_t base, size_ in mvebu_mbus_find_window()
200 mvebu_mbus_read_window(struct mvebu_mbus_state *mbus, int win, int *enabled, u64 *base, u32 *size, u8 *target, u8 *attr, u64 *remap) mvebu_mbus_read_window() argument
271 mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, u8 target, u8 attr) mvebu_mbus_window_conflicts() argument
304 mvebu_mbus_find_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size) mvebu_mbus_find_window() argument
328 mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus, int win, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) mvebu_mbus_setup_window() argument
373 mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus, phys_addr_t base, size_t size, phys_addr_t remap, u8 target, u8 attr) mvebu_mbus_alloc_window() argument
419 u64 base; mvebu_sdram_debug_show_orion() local
448 u64 base; mvebu_sdram_debug_show_dove() local
652 u64 base, size, end; mvebu_mbus_setup_cpu_target_nooverlap() local
704 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); mvebu_mbus_default_setup_cpu_target() local
736 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i)); mvebu_mbus_default_save_cpu_target() local
902 mvebu_mbus_add_window_remap_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size, phys_addr_t remap) mvebu_mbus_add_window_remap_by_id() argument
918 mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute, phys_addr_t base, size_t size) mvebu_mbus_add_window_by_id() argument
925 mvebu_mbus_del_window(phys_addr_t base, size_t size) mvebu_mbus_del_window() argument
1183 mbus_dt_setup_win(struct mvebu_mbus_state *mbus, u32 base, u32 size, u8 target, u8 attr) mbus_dt_setup_win() argument
1252 u32 windowid, base, size; mbus_dt_setup() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/ttm/
H A Dttm_bo.c163 dma_resv_assert_held(bo->base.resv); in ttm_bo_move_to_lru_tail()
197 dma_resv_assert_held(pos->first->base.resv); in ttm_bo_bulk_move_lru_tail()
198 dma_resv_assert_held(pos->last->base.resv); in ttm_bo_bulk_move_lru_tail()
212 dma_resv_assert_held(pos->first->base.resv); in ttm_bo_bulk_move_lru_tail()
213 dma_resv_assert_held(pos->last->base.resv); in ttm_bo_bulk_move_lru_tail()
227 dma_resv_assert_held(pos->first->base.resv); in ttm_bo_bulk_move_lru_tail()
228 dma_resv_assert_held(pos->last->base.resv); in ttm_bo_bulk_move_lru_tail()
334 if (bo->base.resv == &bo->base._resv) in ttm_bo_individualize_resv()
337 BUG_ON(!dma_resv_trylock(&bo->base in ttm_bo_individualize_resv()
[all...]
/kernel/linux/linux-6.6/drivers/spi/
H A Dspi-intel.c21 /* Offsets are from @ispi->base */
143 * @base: Beginning of MMIO space
161 void __iomem *base; member
194 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); in intel_spi_dump_regs()
196 value = readl(ispi->base + HSFSTS_CTL); in intel_spi_dump_regs()
201 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); in intel_spi_dump_regs()
202 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); in intel_spi_dump_regs()
206 i, readl(ispi->base + FDATA(i))); in intel_spi_dump_regs()
208 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); in intel_spi_dump_regs()
212 readl(ispi->base in intel_spi_dump_regs()
233 u32 base, limit; intel_spi_dump_regs() local
249 u32 region, base, limit; intel_spi_dump_regs() local
1191 intel_spi_is_protected(const struct intel_spi *ispi, unsigned int base, unsigned int limit) intel_spi_is_protected() argument
1234 u32 region, base, limit; intel_spi_fill_partition() local
[all...]
/third_party/mesa3d/src/intel/tools/
H A Daubinator_viewer.cpp249 struct window base; member
265 struct window base; member
271 struct window base; member
279 struct window base; member
288 struct window base; member
382 snprintf(window->base.name, sizeof(window->base.name), in new_shader_window()
385 list_inithead(&window->base.parent_link); in new_shader_window()
386 window->base.position = ImVec2(-1, -1); in new_shader_window()
387 window->base in new_shader_window()
[all...]
/kernel/linux/linux-5.10/drivers/fsi/
H A Dfsi-master-aspeed.c25 void __iomem *base; member
100 void __iomem *base = aspeed->base; in __opb_write() local
104 writel(CMD_WRITE, base + OPB0_RW); in __opb_write()
105 writel(transfer_size, base + OPB0_XFER_SIZE); in __opb_write()
106 writel(addr, base + OPB0_FSI_ADDR); in __opb_write()
107 writel(val, base + OPB0_FSI_DATA_W); in __opb_write()
108 writel(0x1, base + OPB_IRQ_CLEAR); in __opb_write()
109 writel(0x1, base + OPB_TRIGGER); in __opb_write()
111 ret = readl_poll_timeout(base in __opb_write()
148 void __iomem *base = aspeed->base; __opb_read() local
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