Lines Matching refs:base
130 u32 base;
201 int win, int *enabled, u64 *base,
216 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
217 *base |= (basereg & WIN_BASE_LOW);
268 * Checks whether the given (base, base+size) area doesn't overlap an
272 phys_addr_t base, size_t size,
275 u64 end = (u64)base + size;
297 if ((u64)base < wend && end > wbase)
305 phys_addr_t base, size_t size)
321 if (base == wbase && size == wsize)
329 int win, phys_addr_t base, size_t size,
342 if ((base & (phys_addr_t)(size - 1)) != 0) {
343 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
355 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
363 remap_addr = base;
374 phys_addr_t base, size_t size,
386 return mvebu_mbus_setup_window(mbus, win, base,
399 return mvebu_mbus_setup_window(mbus, win, base, size,
419 u64 base;
427 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
428 base |= basereg & DDR_BASE_CS_LOW_MASK;
432 i, (unsigned long long)base,
433 (unsigned long long)base + size + 1,
448 u64 base;
456 base = map & 0xff800000;
460 i, (unsigned long long)base,
461 (unsigned long long)base + size, i);
511 seq_puts(seq, " (Invalid base/size!!)");
550 * base, remap low, remap high)
552 * the internal registers base address and internal units
556 * (ctrl, base).
652 u64 base, size, end;
655 base = w->base;
657 end = base + size;
663 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
668 * base address, and shrink its size.
670 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
671 size -= mbus_bridge_end - base;
672 base = mbus_bridge_end;
679 if (base < mbus_bridge_base && end > mbus_bridge_base)
687 w->base = base;
704 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
709 * select is enabled, and that don't have high base
714 !(base & DDR_BASE_CS_HIGH_MASK)) {
722 w->base = base & DDR_BASE_CS_LOW_MASK;
736 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
741 writel(base, store_addr++);
773 w->base = map & 0xff800000;
904 phys_addr_t base, size_t size,
909 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
915 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
919 phys_addr_t base, size_t size)
921 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
925 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
929 win = mvebu_mbus_find_window(&mbus_state, base, size);
967 if (cs->base <= phyaddr &&
968 phyaddr <= (cs->base + cs->size - 1)) {
1008 * If no base has been initialized, doesn't make sense to
1042 s->wins[win].base = readl(addr + WIN_BASE_OFF);
1078 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1184 u32 base, u32 size,
1187 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1193 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1252 u32 windowid, base, size;
1266 base = of_read_number(r + c_addr_cells, addr_cells);
1269 ret = mbus_dt_setup_win(mbus, base, size, target, attr);