Lines Matching refs:base
25 void __iomem *base;
100 void __iomem *base = aspeed->base;
104 writel(CMD_WRITE, base + OPB0_RW);
105 writel(transfer_size, base + OPB0_XFER_SIZE);
106 writel(addr, base + OPB0_FSI_ADDR);
107 writel(val, base + OPB0_FSI_DATA_W);
108 writel(0x1, base + OPB_IRQ_CLEAR);
109 writel(0x1, base + OPB_TRIGGER);
111 ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
115 status = readl(base + OPB0_STATUS);
148 void __iomem *base = aspeed->base;
152 writel(CMD_READ, base + OPB0_RW);
153 writel(transfer_size, base + OPB0_XFER_SIZE);
154 writel(addr, base + OPB0_FSI_ADDR);
155 writel(0x1, base + OPB_IRQ_CLEAR);
156 writel(0x1, base + OPB_TRIGGER);
158 ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg,
162 status = readl(base + OPB0_STATUS);
164 result = readl(base + OPB0_FSI_DATA_R);
167 readl(base + OPB0_STATUS),
545 aspeed->base = devm_platform_ioremap_resource(pdev, 0);
546 if (IS_ERR(aspeed->base)) {
547 rc = PTR_ERR(aspeed->base);
568 writel(0x1, aspeed->base + OPB_CLK_SYNC);
570 aspeed->base + OPB_IRQ_MASK);
573 writel(0x10, aspeed->base + OPB_RETRY_COUNTER);
575 writel(ctrl_base, aspeed->base + OPB_CTRL_BASE);
576 writel(fsi_base, aspeed->base + OPB_FSI_BASE);
579 writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1);
582 writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1);
583 writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2);
590 writel(0x1, aspeed->base + OPB0_SELECT);