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/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-tpda.c29 val = readl_relaxed(drvdata->base + TPDA_CR); in tpda_enable_pre_port()
32 writel_relaxed(val, drvdata->base + TPDA_CR); in tpda_enable_pre_port()
39 val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); in tpda_enable_port()
42 writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); in tpda_enable_port()
47 CS_UNLOCK(drvdata->base); in __tpda_enable()
54 CS_LOCK(drvdata->base); in __tpda_enable()
78 CS_UNLOCK(drvdata->base); in __tpda_disable()
80 val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port)); in __tpda_disable()
82 writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port)); in __tpda_disable()
84 CS_LOCK(drvdata->base); in __tpda_disable()
136 void __iomem *base; tpda_probe() local
[all...]
/kernel/linux/linux-6.6/drivers/irqchip/
H A Dirq-al-fic.c37 void __iomem *base; member
49 u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
60 writel_relaxed(control, fic->base + AL_FIC_CONTROL); in al_fic_set_trigger()
117 pending = readl_relaxed(fic->base + AL_FIC_CAUSE); in al_fic_irq_handler()
131 writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE); in al_fic_irq_retrigger()
162 gc->reg_base = fic->base; in al_fic_register()
187 * @base: mmio to fic register
197 void __iomem *base, in al_fic_wire_init()
209 fic->base = base; in al_fic_wire_init()
196 al_fic_wire_init(struct device_node *node, void __iomem *base, const char *name, unsigned int parent_irq) al_fic_wire_init() argument
241 void __iomem *base; al_fic_init_dt() local
[all...]
/third_party/mesa3d/src/freedreno/decode/scripts/
H A Dtexturator-to-unit-test.lua5 -- texture state. This gives us the base address, and the miplevel #0
20 function get_next_blit(base, width, height, prev_blit)
25 if blit.base == base and blit.width == width and blit.height == height and (not prev_blit or prev_blit.addr < blit.addr) then
35 function get_first_blit(base, width, height)
36 return get_next_blit(base, width, height, nil);
84 blit.base = bos.base(blit.addr)
85 blit.ubwc_base = bos.base(blit.uwbc_addr)
89 type, blit.addr, blit.pitch, blit.base, bli
[all...]
/third_party/node/deps/v8/src/heap/
H A Dcode-range.cc7 #include "src/base/bits.h"
8 #include "src/base/lazy-instance.h"
20 base::LazyMutex process_wide_code_range_creation_mutex_ =
26 base::LazyInstance<std::weak_ptr<CodeRange>>::type process_wide_code_range_ =
36 base::MutexGuard guard(&mutex_); in GetAddressHint()
40 base::AddressRegion preferred_region = Isolate::GetShortBuiltinsCallRegion(); in GetAddressHint()
48 auto memory_ranges = base::OS::GetFreeMemoryRangesWithin( in GetAddressHint()
74 freed_regions_for_size.erase((it_freed + 1).base()); in GetAddressHint()
88 base::MutexGuard guard(&mutex_); in NotifyFreedCodeRange()
128 ? base in InitReservation()
141 Address base = page_allocator_->begin(); InitReservation() local
[all...]
/kernel/linux/linux-5.10/drivers/crypto/inside-secure/
H A Dsafexcel_cipher.c45 struct safexcel_context base; member
376 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_skcipher_aes_setkey()
384 if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { in safexcel_skcipher_aes_setkey()
387 ctx->base.needs_inv = true; in safexcel_skcipher_aes_setkey()
407 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_aead_setkey()
453 if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { in safexcel_aead_setkey()
457 ctx->base.needs_inv = true; in safexcel_aead_setkey()
488 if (safexcel_hmac_setkey(&ctx->base, keys.authkey, keys.authkeylen, in safexcel_aead_setkey()
510 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_context_control()
667 static int safexcel_send_req(struct crypto_async_request *base, in argument
896 safexcel_handle_inv_result(struct safexcel_crypto_priv *priv, int ring, struct crypto_async_request *base, struct safexcel_cipher_req *sreq, bool *should_complete, int *ret) safexcel_handle_inv_result() argument
1001 safexcel_cipher_send_inv(struct crypto_async_request *base, int ring, int *commands, int *results) safexcel_cipher_send_inv() argument
1073 safexcel_cipher_exit_inv(struct crypto_tfm *tfm, struct crypto_async_request *base, struct safexcel_cipher_req *sreq, struct safexcel_inv_result *result) safexcel_cipher_exit_inv() argument
1137 safexcel_queue_req(struct crypto_async_request *base, struct safexcel_cipher_req *sreq, enum safexcel_cipher_direction dir) safexcel_queue_req() argument
[all...]
/kernel/linux/linux-6.6/drivers/crypto/inside-secure/
H A Dsafexcel_cipher.c46 struct safexcel_context base; member
376 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_skcipher_aes_setkey()
384 if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { in safexcel_skcipher_aes_setkey()
387 ctx->base.needs_inv = true; in safexcel_skcipher_aes_setkey()
407 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_aead_setkey()
453 if (priv->flags & EIP197_TRC_CACHE && ctx->base.ctxr_dma) { in safexcel_aead_setkey()
457 ctx->base.needs_inv = true; in safexcel_aead_setkey()
488 if (safexcel_hmac_setkey(&ctx->base, keys.authkey, keys.authkeylen, in safexcel_aead_setkey()
510 struct safexcel_crypto_priv *priv = ctx->base.priv; in safexcel_context_control()
673 static int safexcel_send_req(struct crypto_async_request *base, in argument
917 safexcel_handle_inv_result(struct safexcel_crypto_priv *priv, int ring, struct crypto_async_request *base, struct safexcel_cipher_req *sreq, bool *should_complete, int *ret) safexcel_handle_inv_result() argument
1022 safexcel_cipher_send_inv(struct crypto_async_request *base, int ring, int *commands, int *results) safexcel_cipher_send_inv() argument
1094 safexcel_cipher_exit_inv(struct crypto_tfm *tfm, struct crypto_async_request *base, struct safexcel_cipher_req *sreq, struct crypto_wait *result) safexcel_cipher_exit_inv() argument
1157 safexcel_queue_req(struct crypto_async_request *base, struct safexcel_cipher_req *sreq, enum safexcel_cipher_direction dir) safexcel_queue_req() argument
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/kernel/linux/linux-5.10/drivers/vme/bridges/
H A Dvme_tsi148.c127 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
148 ioread32be(bridge->base + TSI148_LCSR_EDPAU), in tsi148_PERR_irqhandler()
149 ioread32be(bridge->base + TSI148_LCSR_EDPAL), in tsi148_PERR_irqhandler()
150 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); in tsi148_PERR_irqhandler()
154 ioread32be(bridge->base + TSI148_LCSR_EDPXA), in tsi148_PERR_irqhandler()
155 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); in tsi148_PERR_irqhandler()
157 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); in tsi148_PERR_irqhandler()
175 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); in tsi148_VERR_irqhandler()
176 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); in tsi148_VERR_irqhandler()
177 error_attrib = ioread32be(bridge->base in tsi148_VERR_irqhandler()
[all...]
/kernel/linux/linux-6.6/drivers/staging/vme_user/
H A Dvme_tsi148.c126 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); in tsi148_MB_irqhandler()
146 ioread32be(bridge->base + TSI148_LCSR_EDPAU), in tsi148_PERR_irqhandler()
147 ioread32be(bridge->base + TSI148_LCSR_EDPAL), in tsi148_PERR_irqhandler()
148 ioread32be(bridge->base + TSI148_LCSR_EDPAT)); in tsi148_PERR_irqhandler()
151 ioread32be(bridge->base + TSI148_LCSR_EDPXA), in tsi148_PERR_irqhandler()
152 ioread32be(bridge->base + TSI148_LCSR_EDPXS)); in tsi148_PERR_irqhandler()
154 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); in tsi148_PERR_irqhandler()
172 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); in tsi148_VERR_irqhandler()
173 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); in tsi148_VERR_irqhandler()
174 error_attrib = ioread32be(bridge->base in tsi148_VERR_irqhandler()
[all...]
/kernel/linux/linux-5.10/drivers/gpio/
H A Dgpio-omap.c48 void __iomem *base; member
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, in omap_set_gpio_dataout_mask()
149 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
161 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
199 writel_relaxed(debounce, bank->base + bank->regs->debounce); in omap2_set_gpio_debounce()
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); in omap2_set_gpio_debounce()
245 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
249 writel_relaxed(bank->context.debounce, bank->base in omap_clear_gpio_debounce()
275 void __iomem *base = bank->base; omap_set_gpio_trigger() local
858 void __iomem *base = bank->base; omap_gpio_get_multiple() local
965 void __iomem *base = bank->base; omap_gpio_mod_init() local
1074 void __iomem *base = p->base; omap_gpio_init_context() local
1094 void __iomem *base = bank->base; omap_gpio_restore_context() local
1119 void __iomem *base = bank->base; omap_gpio_idle() local
[all...]
/kernel/linux/linux-6.6/drivers/gpio/
H A Dgpio-omap.c48 void __iomem *base; member
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
121 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
139 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, in omap_set_gpio_dataout_mask()
150 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
162 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
200 writel_relaxed(debounce, bank->base + bank->regs->debounce); in omap2_set_gpio_debounce()
202 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); in omap2_set_gpio_debounce()
246 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
250 writel_relaxed(bank->context.debounce, bank->base in omap_clear_gpio_debounce()
276 void __iomem *base = bank->base; omap_set_gpio_trigger() local
894 void __iomem *base = bank->base; omap_gpio_get_multiple() local
1001 void __iomem *base = bank->base; omap_gpio_mod_init() local
1093 void __iomem *base = p->base; omap_gpio_init_context() local
1113 void __iomem *base = bank->base; omap_gpio_restore_context() local
1138 void __iomem *base = bank->base; omap_gpio_idle() local
[all...]
/kernel/linux/linux-5.10/arch/arm64/crypto/
H A Dsha512-glue.c62 .base.cra_name = "sha512",
63 .base.cra_driver_name = "sha512-arm64",
64 .base.cra_priority = 150,
65 .base.cra_blocksize = SHA512_BLOCK_SIZE,
66 .base.cra_module = THIS_MODULE,
74 .base.cra_name = "sha384",
75 .base.cra_driver_name = "sha384-arm64",
76 .base.cra_priority = 150,
77 .base.cra_blocksize = SHA384_BLOCK_SIZE,
78 .base
[all...]
/kernel/linux/linux-5.10/arch/mips/pistachio/
H A Dinit.c85 void *base; in mips_nmi_setup() local
88 base = cpu_has_veic ? in mips_nmi_setup()
91 memcpy(base, except_vec_nmi, 0x80); in mips_nmi_setup()
92 flush_icache_range((unsigned long)base, in mips_nmi_setup()
93 (unsigned long)base + 0x80); in mips_nmi_setup()
98 void *base; in mips_ejtag_setup() local
101 base = cpu_has_veic ? in mips_ejtag_setup()
104 memcpy(base, except_vec_ejtag_debug, 0x80); in mips_ejtag_setup()
105 flush_icache_range((unsigned long)base, in mips_ejtag_setup()
106 (unsigned long)base in mips_ejtag_setup()
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/kernel/linux/linux-5.10/arch/x86/include/asm/
H A Dmtrr.h38 extern int mtrr_add(unsigned long base, unsigned long size,
40 extern int mtrr_add_page(unsigned long base, unsigned long size,
42 extern int mtrr_del(int reg, unsigned long base, unsigned long size);
43 extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
62 static inline int mtrr_add(unsigned long base, unsigned long size, in mtrr_add() argument
67 static inline int mtrr_add_page(unsigned long base, unsigned long size, in mtrr_add_page() argument
72 static inline int mtrr_del(int reg, unsigned long base, unsigned long size) in mtrr_del() argument
76 static inline int mtrr_del_page(int reg, unsigned long base, unsigned long size) in mtrr_del_page() argument
102 compat_ulong_t base; /* Base address */ member
109 compat_uint_t base; /* Bas member
[all...]
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-moxart.c21 void __iomem *base; in moxart_of_pll_clk_init() local
31 base = of_iomap(node, 0); in moxart_of_pll_clk_init()
32 if (!base) { in moxart_of_pll_clk_init()
37 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
38 iounmap(base); in moxart_of_pll_clk_init()
60 void __iomem *base; in moxart_of_apb_clk_init() local
71 base = of_iomap(node, 0); in moxart_of_apb_clk_init()
72 if (!base) { in moxart_of_apb_clk_init()
77 val = readl(base + 0xc) >> 4 & 0x7; in moxart_of_apb_clk_init()
78 iounmap(base); in moxart_of_apb_clk_init()
[all...]
/kernel/linux/linux-6.6/arch/arm64/crypto/
H A Dsha512-glue.c62 .base.cra_name = "sha512",
63 .base.cra_driver_name = "sha512-arm64",
64 .base.cra_priority = 150,
65 .base.cra_blocksize = SHA512_BLOCK_SIZE,
66 .base.cra_module = THIS_MODULE,
74 .base.cra_name = "sha384",
75 .base.cra_driver_name = "sha384-arm64",
76 .base.cra_priority = 150,
77 .base.cra_blocksize = SHA384_BLOCK_SIZE,
78 .base
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dgen6_ppgtt.h14 struct i915_ppgtt base; member
42 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_ppgtt, base)
44 static inline struct gen6_ppgtt *to_gen6_ppgtt(struct i915_ppgtt *base) in to_gen6_ppgtt() argument
46 BUILD_BUG_ON(offsetof(struct gen6_ppgtt, base)); in to_gen6_ppgtt()
47 return __to_gen6_ppgtt(base); in to_gen6_ppgtt()
72 int gen6_ppgtt_pin(struct i915_ppgtt *base, struct i915_gem_ww_ctx *ww);
73 void gen6_ppgtt_unpin(struct i915_ppgtt *base);
74 void gen6_ppgtt_unpin_all(struct i915_ppgtt *base);
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/
H A Dnv10_fence.c38 PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno); in nv10_fence_emit()
62 nouveau_fence_context_del(&fctx->base); in nv10_fence_context_del()
65 nouveau_fence_context_free(&fctx->base); in nv10_fence_context_del()
77 nouveau_fence_context_new(chan, &fctx->base); in nv10_fence_context_new()
78 fctx->base.emit = nv10_fence_emit; in nv10_fence_context_new()
79 fctx->base.read = nv10_fence_read; in nv10_fence_context_new()
80 fctx->base.sync = nv10_fence_sync; in nv10_fence_context_new()
105 priv->base.dtor = nv10_fence_destroy; in nv10_fence_create()
106 priv->base.context_new = nv10_fence_context_new; in nv10_fence_create()
107 priv->base in nv10_fence_create()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgp100.c49 gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) in gp100_ce_intr_launcherr() argument
53 u32 stat = nvkm_rd32(device, 0x104418 + base); in gp100_ce_intr_launcherr()
62 const u32 base = (ce->subdev.index - NVKM_ENGINE_CE0) * 0x80; in gp100_ce_intr() local
65 u32 mask = nvkm_rd32(device, 0x10440c + base); in gp100_ce_intr()
66 u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; in gp100_ce_intr()
69 nvkm_wr32(device, 0x104410 + base, 0x00000001); in gp100_ce_intr()
74 nvkm_wr32(device, 0x104410 + base, 0x00000002); in gp100_ce_intr()
78 gp100_ce_intr_launcherr(ce, base); in gp100_ce_intr()
79 nvkm_wr32(device, 0x104410 + base, 0x00000004); in gp100_ce_intr()
84 nvkm_wr32(device, 0x104410 + base, int in gp100_ce_intr()
[all...]
/kernel/linux/linux-5.10/drivers/staging/media/tegra-vde/
H A Dvde.h75 tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) in tegra_vde_reg_base_name() argument
77 if (vde->sxe == base) in tegra_vde_reg_base_name()
80 if (vde->bsev == base) in tegra_vde_reg_base_name()
83 if (vde->mbe == base) in tegra_vde_reg_base_name()
86 if (vde->ppe == base) in tegra_vde_reg_base_name()
89 if (vde->mce == base) in tegra_vde_reg_base_name()
92 if (vde->tfe == base) in tegra_vde_reg_base_name()
95 if (vde->ppb == base) in tegra_vde_reg_base_name()
98 if (vde->vdma == base) in tegra_vde_reg_base_name()
101 if (vde->frameid == base) in tegra_vde_reg_base_name()
[all...]
/kernel/linux/linux-6.6/drivers/misc/
H A Dsram-exec.c25 unsigned long base = (unsigned long)part->base; in sram_check_protect_exec() local
26 unsigned long end = base + block->size; in sram_check_protect_exec()
28 if (!PAGE_ALIGNED(base) || !PAGE_ALIGNED(end)) { in sram_check_protect_exec()
77 unsigned long base; in sram_exec_copy() local
95 base = (unsigned long)part->base; in sram_exec_copy()
100 ret = set_memory_nx((unsigned long)base, pages); in sram_exec_copy()
103 ret = set_memory_rw((unsigned long)base, pages); in sram_exec_copy()
109 ret = set_memory_rox((unsigned long)base, page in sram_exec_copy()
[all...]
/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-moxart.c18 void __iomem *base; in moxart_of_pll_clk_init() local
28 base = of_iomap(node, 0); in moxart_of_pll_clk_init()
29 if (!base) { in moxart_of_pll_clk_init()
34 mul = readl(base + 0x30) >> 3 & 0x3f; in moxart_of_pll_clk_init()
35 iounmap(base); in moxart_of_pll_clk_init()
57 void __iomem *base; in moxart_of_apb_clk_init() local
68 base = of_iomap(node, 0); in moxart_of_apb_clk_init()
69 if (!base) { in moxart_of_apb_clk_init()
74 val = readl(base + 0xc) >> 4 & 0x7; in moxart_of_apb_clk_init()
75 iounmap(base); in moxart_of_apb_clk_init()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgp100.c49 gp100_ce_intr_launcherr(struct nvkm_engine *ce, const u32 base) in gp100_ce_intr_launcherr() argument
53 u32 stat = nvkm_rd32(device, 0x104418 + base); in gp100_ce_intr_launcherr()
64 const u32 base = subdev->inst * 0x80; in gp100_ce_intr() local
65 u32 mask = nvkm_rd32(device, 0x10440c + base); in gp100_ce_intr()
66 u32 intr = nvkm_rd32(device, 0x104410 + base) & mask; in gp100_ce_intr()
69 nvkm_wr32(device, 0x104410 + base, 0x00000001); in gp100_ce_intr()
74 nvkm_wr32(device, 0x104410 + base, 0x00000002); in gp100_ce_intr()
78 gp100_ce_intr_launcherr(ce, base); in gp100_ce_intr()
79 nvkm_wr32(device, 0x104410 + base, 0x00000004); in gp100_ce_intr()
84 nvkm_wr32(device, 0x104410 + base, int in gp100_ce_intr()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/
H A Dnv10_fence.c38 PUSH_MTHD(push, NV06E, SET_REFERENCE, fence->base.seqno); in nv10_fence_emit()
62 nouveau_fence_context_del(&fctx->base); in nv10_fence_context_del()
65 nouveau_fence_context_free(&fctx->base); in nv10_fence_context_del()
77 nouveau_fence_context_new(chan, &fctx->base); in nv10_fence_context_new()
78 fctx->base.emit = nv10_fence_emit; in nv10_fence_context_new()
79 fctx->base.read = nv10_fence_read; in nv10_fence_context_new()
80 fctx->base.sync = nv10_fence_sync; in nv10_fence_context_new()
105 priv->base.dtor = nv10_fence_destroy; in nv10_fence_create()
106 priv->base.context_new = nv10_fence_context_new; in nv10_fence_create()
107 priv->base in nv10_fence_create()
[all...]
/third_party/node/deps/v8/src/diagnostics/
H A Dcode-tracer.h8 #include "src/base/optional.h"
9 #include "src/base/platform/wrappers.h"
10 #include "src/base/strings.h"
11 #include "src/base/vector.h"
30 base::StrNCpy(filename_, FLAG_redirect_code_traces_to, in CodeTracer()
33 base::SNPrintF(filename_, "code-%d-%d.asm", in CodeTracer()
34 base::OS::GetCurrentProcessId(), isolate_id); in CodeTracer()
36 base::SNPrintF(filename_, "code-%d.asm", base::OS::GetCurrentProcessId()); in CodeTracer()
71 base
[all...]
/third_party/skia/third_party/externals/dawn/src/tests/unittests/
H A DToBackendTests.cpp41 // Test that ToBackend correctly converts pointers to base classes.
45 const AdapterBase* base = adapter; in TEST() local
47 auto backendAdapter = ToBackend(base); in TEST()
55 AdapterBase* base = adapter; in TEST() local
57 auto backendAdapter = ToBackend(base); in TEST()
65 // Test that ToBackend correctly converts Refs to base classes.
69 const Ref<AdapterBase> base(adapter); in TEST()
71 const auto& backendAdapter = ToBackend(base); in TEST()
72 static_assert(std::is_same<decltype(ToBackend(base)), const Ref<MyAdapter>&>::value, ""); in TEST()
79 Ref<AdapterBase> base(adapte in TEST()
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