Lines Matching refs:base
127 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
148 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
149 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
150 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
154 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
155 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
157 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
175 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
176 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
177 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
196 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
229 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
255 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
256 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
299 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
359 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
360 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
371 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
372 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
375 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
388 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
410 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
412 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
423 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
425 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
448 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
453 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
457 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
525 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
539 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
542 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
546 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
548 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
550 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
552 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
554 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
556 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
601 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
607 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
632 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
635 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
637 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
639 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
641 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
643 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
645 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
882 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
903 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
906 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1008 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
1010 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
1012 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
1014 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
1016 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
1018 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
1022 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1028 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
1065 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1068 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1070 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1072 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1074 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1076 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1078 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1384 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1386 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
1393 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1394 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1395 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1396 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1397 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
1400 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1402 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1408 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
1410 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
1793 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1849 iowrite32be(bus_addr_high, bridge->base +
1851 iowrite32be(bus_addr_low, bridge->base +
1854 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1858 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
1865 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +
1878 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1921 * All 4 location monitors reside at the same base - this is therefore a
1982 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1983 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1984 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2004 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2005 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2006 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2059 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2079 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2081 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
2083 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2085 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2090 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
2111 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
2113 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
2115 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
2117 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
2120 bridge->base + TSI148_LCSR_INTC);
2129 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
2131 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
2150 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
2213 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2214 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
2217 cbar = ioread32be(bridge->base + TSI148_CBAR);
2225 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
2229 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2235 bridge->base + TSI148_LCSR_CRAT);
2264 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2266 bridge->base + TSI148_LCSR_CRAT);
2269 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2270 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
2321 tsi148_device->base = ioremap(pci_resource_start(pdev, 0),
2323 if (!tsi148_device->base) {
2330 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
2480 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2508 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
2511 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
2551 iounmap(tsi148_device->base);
2585 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
2587 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
2594 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
2599 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
2604 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2605 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2606 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
2611 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2612 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
2617 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2618 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
2648 iounmap(bridge->base);