Lines Matching refs:base
48 void __iomem *base;
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
120 void __iomem *reg = bank->base;
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
149 bank->base + bank->regs->debounce_en);
161 writel_relaxed(0, bank->base + bank->regs->debounce_en);
199 writel_relaxed(debounce, bank->base + bank->regs->debounce);
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
245 bank->base + bank->regs->debounce_en);
249 writel_relaxed(bank->context.debounce, bank->base +
275 void __iomem *base = bank->base;
278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
294 readl_relaxed(bank->base + bank->regs->leveldetect0);
296 readl_relaxed(bank->base + bank->regs->leveldetect1);
298 readl_relaxed(bank->base + bank->regs->risingdetect);
300 readl_relaxed(bank->base + bank->regs->fallingdetect);
327 void __iomem *reg = bank->base + bank->regs->irqctrl;
336 void __iomem *reg = bank->base;
376 void __iomem *reg = bank->base + bank->regs->pinctrl;
383 void __iomem *reg = bank->base + bank->regs->ctrl;
397 void __iomem *reg = bank->base + bank->regs->ctrl;
410 void __iomem *reg = bank->base + bank->regs->direction;
471 void __iomem *reg = bank->base;
478 reg = bank->base + bank->regs->irqstatus2;
494 void __iomem *reg = bank->base;
509 void __iomem *reg = bank->base;
536 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
567 isr_reg = bank->base + bank->regs->irqstatus;
717 void __iomem *mask_reg = bank->base +
731 void __iomem *mask_reg = bank->base +
810 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
834 reg = bank->base + bank->regs->datain;
836 reg = bank->base + bank->regs->dataout;
858 void __iomem *base = bank->base;
861 direction = readl_relaxed(base + bank->regs->direction);
865 val |= readl_relaxed(base + bank->regs->datain) & m;
869 val |= readl_relaxed(base + bank->regs->dataout) & m;
935 void __iomem *reg = bank->base + bank->regs->dataout;
956 rev = readw_relaxed(bank->base + bank->regs->revision);
965 void __iomem *base = bank->base;
972 writel_relaxed(l, bank->base + bank->regs->irqenable);
976 omap_gpio_rmw(base + bank->regs->irqenable, l,
978 omap_gpio_rmw(base + bank->regs->irqstatus, l,
981 writel_relaxed(0, base + bank->regs->debounce_en);
984 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
987 writel_relaxed(0, base + bank->regs->ctrl);
1016 bank->chip.base = OMAP_MPUIO(0);
1023 bank->chip.base = gpio;
1030 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1074 void __iomem *base = p->base;
1076 p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
1077 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1078 p->context.oe = readl_relaxed(base + regs->direction);
1079 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1080 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1081 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1082 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1083 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1084 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1085 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1086 p->context.dataout = readl_relaxed(base + regs->dataout);
1094 void __iomem *base = bank->base;
1096 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1097 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1098 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1099 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1100 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1101 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1102 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1103 writel_relaxed(bank->context.dataout, base + regs->dataout);
1104 writel_relaxed(bank->context.oe, base + regs->direction);
1107 writel_relaxed(bank->context.debounce, base + regs->debounce);
1109 base + regs->debounce_en);
1112 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1113 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1119 void __iomem *base = bank->base;
1122 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1126 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1151 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1152 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1198 bank->base + bank->regs->fallingdetect);
1200 bank->base + bank->regs->risingdetect);
1203 l = readl_relaxed(bank->base + bank->regs->datain);
1233 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1234 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1237 writel_relaxed(old0 | gen, bank->base +
1239 writel_relaxed(old1 | gen, bank->base +
1244 writel_relaxed(old0 | l, bank->base +
1246 writel_relaxed(old1 | l, bank->base +
1249 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1250 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1271 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1451 bank->base = devm_platform_ioremap_resource(pdev, 0);
1452 if (IS_ERR(bank->base)) {
1453 return PTR_ERR(bank->base);