Lines Matching refs:base
48 void __iomem *base;
112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
121 void __iomem *reg = bank->base;
139 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
150 bank->base + bank->regs->debounce_en);
162 writel_relaxed(0, bank->base + bank->regs->debounce_en);
200 writel_relaxed(debounce, bank->base + bank->regs->debounce);
202 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
246 bank->base + bank->regs->debounce_en);
250 writel_relaxed(bank->context.debounce, bank->base +
276 void __iomem *base = bank->base;
279 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
281 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
289 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
291 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
295 readl_relaxed(bank->base + bank->regs->leveldetect0);
297 readl_relaxed(bank->base + bank->regs->leveldetect1);
299 readl_relaxed(bank->base + bank->regs->risingdetect);
301 readl_relaxed(bank->base + bank->regs->fallingdetect);
328 void __iomem *reg = bank->base + bank->regs->irqctrl;
337 void __iomem *reg = bank->base;
377 void __iomem *reg = bank->base + bank->regs->pinctrl;
384 void __iomem *reg = bank->base + bank->regs->ctrl;
398 void __iomem *reg = bank->base + bank->regs->ctrl;
411 void __iomem *reg = bank->base + bank->regs->direction;
472 void __iomem *reg = bank->base;
479 reg = bank->base + bank->regs->irqstatus2;
495 void __iomem *reg = bank->base;
510 void __iomem *reg = bank->base;
537 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
568 isr_reg = bank->base + bank->regs->irqstatus;
753 void __iomem *mask_reg = bank->base +
767 void __iomem *mask_reg = bank->base +
846 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
870 reg = bank->base + bank->regs->datain;
872 reg = bank->base + bank->regs->dataout;
894 void __iomem *base = bank->base;
897 direction = readl_relaxed(base + bank->regs->direction);
901 val |= readl_relaxed(base + bank->regs->datain) & m;
905 val |= readl_relaxed(base + bank->regs->dataout) & m;
971 void __iomem *reg = bank->base + bank->regs->dataout;
992 rev = readw_relaxed(bank->base + bank->regs->revision);
1001 void __iomem *base = bank->base;
1008 writel_relaxed(l, bank->base + bank->regs->irqenable);
1012 omap_gpio_rmw(base + bank->regs->irqenable, l,
1014 omap_gpio_rmw(base + bank->regs->irqstatus, l,
1017 writel_relaxed(0, base + bank->regs->debounce_en);
1020 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1023 writel_relaxed(0, base + bank->regs->ctrl);
1051 bank->chip.base = OMAP_MPUIO(0);
1058 bank->chip.base = -1;
1093 void __iomem *base = p->base;
1095 p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
1096 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1097 p->context.oe = readl_relaxed(base + regs->direction);
1098 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1099 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1100 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1101 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1102 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1103 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1104 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1105 p->context.dataout = readl_relaxed(base + regs->dataout);
1113 void __iomem *base = bank->base;
1115 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1116 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1117 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1118 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1119 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1120 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1121 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1122 writel_relaxed(bank->context.dataout, base + regs->dataout);
1123 writel_relaxed(bank->context.oe, base + regs->direction);
1126 writel_relaxed(bank->context.debounce, base + regs->debounce);
1128 base + regs->debounce_en);
1131 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1132 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1138 void __iomem *base = bank->base;
1141 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1145 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1170 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1171 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1217 bank->base + bank->regs->fallingdetect);
1219 bank->base + bank->regs->risingdetect);
1222 l = readl_relaxed(bank->base + bank->regs->datain);
1252 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1253 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1256 writel_relaxed(old0 | gen, bank->base +
1258 writel_relaxed(old1 | gen, bank->base +
1263 writel_relaxed(old0 | l, bank->base +
1265 writel_relaxed(old1 | l, bank->base +
1268 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1269 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1290 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1447 bank->base = devm_platform_ioremap_resource(pdev, 0);
1448 if (IS_ERR(bank->base)) {
1449 return PTR_ERR(bank->base);