| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/gem/selftests/ |
| H A D | i915_gem_mman.c | 36 unsigned int swizzle; member
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| /third_party/astc-encoder/Source/ |
| H A D | astcenc_entry.cpp | 826 compress_image( astcenc_context& ctxo, unsigned int thread_index, const astcenc_image& image, const astcenc_swizzle& swizzle, uint8_t* buffer, bool calQualityEnable, int32_t *mse[RGBA_COM] ) compress_image() argument
1060 astcenc_compress_image( astcenc_context* ctxo, astcenc_image* imagep, const astcenc_swizzle* swizzle, uint8_t* data_out, size_t data_len, bool calQualityEnable, int32_t *mse[RGBA_COM], unsigned int thread_index ) astcenc_compress_image() argument
1186 astcenc_decompress_image( astcenc_context* ctxo, const uint8_t* data, size_t data_len, astcenc_image* image_outp, const astcenc_swizzle* swizzle, unsigned int thread_index ) astcenc_decompress_image() argument
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| /third_party/mesa3d/src/compiler/nir/ |
| H A D | nir_split_vars.c | 1583 unsigned swizzle[NIR_MAX_VEC_COMPONENTS]; in shrink_vec_var_access_impl() local
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| H A D | nir.h | 177 uint16_t swizzle; member
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| H A D | nir_builder.h | 499 unsigned num_channels = 0, swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 }; in nir_channels() local
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| /third_party/mesa3d/src/broadcom/vulkan/ |
| H A D | v3dvx_meta_common.c | 315 const uint8_t *swizzle = v3dv_get_format_swizzle(device, format); in format_needs_rb_swap() local
323 const uint8_t *swizzle = v3dv_get_format_swizzle(device, format); in format_needs_reverse() local
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| /third_party/mesa3d/src/compiler/glsl/ |
| H A D | glsl_to_nir.cpp | 1253 ir_swizzle *swizzle = NULL; in visit() local
1877 ir_swizzle *swizzle = NULL; visit() local
2393 unsigned swizzle[4] = { ir->mask.x, ir->mask.y, ir->mask.z, ir->mask.w }; visit() local
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm.c | 383 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx, unsigned swizzle) in si_get_primitive_id() argument
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| H A D | si_clear.c | 309 unsigned swizzle = desc->swizzle[i]; in gfx11_get_dcc_clear_parameters() local
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_nir_lower_64bit.cpp | 1098 int swizzle[NIR_MAX_VEC_COMPONENTS] = {0}; in r600_nir_64_to_vec2() local
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| H A D | ShaderTGSI.c | 413 const struct swizzle_mapping *swizzle = in swizzle_reg() local
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| /third_party/mesa3d/src/intel/blorp/ |
| H A D | blorp_clear.c | 448 blorp_fast_clear(struct blorp_batch *batch, const struct blorp_surf *surf, enum isl_format format, struct isl_swizzle swizzle, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) blorp_fast_clear() argument
511 blorp_clear(struct blorp_batch *batch, const struct blorp_surf *surf, enum isl_format format, struct isl_swizzle swizzle, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, union isl_color_value clear_color, uint8_t color_write_disable) blorp_clear() argument
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| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_vec4.cpp | 524 unsigned swizzle; in opt_reduce_swizzle() local
847 can_reswizzle(const struct intel_device_info *devinfo, int dst_writemask, int swizzle, int swizzle_mask) can_reswizzle() argument
899 reswizzle(int dst_writemask, int swizzle) reswizzle() argument
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| H A D | brw_vec4_nir.cpp | 769 brw_swizzle_for_nir_swizzle(uint8_t swizzle[4]) brw_swizzle_for_nir_swizzle() argument
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| /third_party/mesa3d/src/mesa/state_tracker/ |
| H A D | st_pbo_compute.c | 850 const uint8_t *swizzle; in download_texture_compute() local
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| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | midgard_schedule.c | 931 mir_schedule_comparison( compiler_context *ctx, midgard_instruction **instructions, struct midgard_predicate *predicate, BITSET_WORD *worklist, unsigned count, unsigned cond, bool vector, unsigned *swizzle, midgard_instruction *user) mir_schedule_comparison() argument
1139 unsigned swizzle = (branch->src[0] == ~0) ? COMPONENT_Y : COMPONENT_X; mir_schedule_zs_write() local
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| H A D | midgard_ra.c | 45 offset_swizzle(unsigned *swizzle, unsigned reg_offset, unsigned srcshift, unsigned dstshift, unsigned dst_offset) in offset_swizzle() argument
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| H A D | midgard_emit.c | 179 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component) in mir_pack_swizzle_64() argument
226 mir_pack_swizzle(unsigned mask, unsigned *swizzle, in mir_pack_swizzle() argument
348 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i], mir_pack_vector_srcs() local
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| H A D | compiler.h | 100 unsigned swizzle[MIR_SRC_COUNT][MIR_VEC_COMPONENTS]; member
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| /third_party/mesa3d/src/util/format/ |
| H A D | u_format.h | 239 unsigned char swizzle[4]; member
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| H A D | lp_bld_tgsi.h | 96 unsigned swizzle:3; /* PIPE_SWIZZLE_x */ member
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_build.c | 904 tgsi_build_ind_register( unsigned file, unsigned swizzle, int index, unsigned arrayid, struct tgsi_instruction *instruction, struct tgsi_header *header ) tgsi_build_ind_register() argument
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| H A D | tgsi_text.c | 900 uint swizzle[4]; in parse_src_operand() local
857 parse_optional_swizzle( struct translate_ctx *ctx, uint *swizzle, boolean *parsed_swizzle, int components) parse_optional_swizzle() argument
976 uint swizzle[3]; parse_texoffset_operand() local
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_compiler_nir.c | 209 src_swizzle(hw_src src, unsigned swizzle) in src_swizzle() argument
759 uint8_t swizzle[4][4] = {}; lower_alu() local
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| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/pipeline/ |
| H A D | vktPipelineImageSamplingInstance.cpp | 1035 tcu::Vector<ScalarType, 4> swizzle (const tcu::Vector<ScalarType, 4>& vec, const vk::VkComponentMapping& swz) in swizzle() function
1094 void swizzle (cons function
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