Lines Matching defs:swizzle
56 this->swizzle = brw_swizzle_for_size(type->vector_elements);
58 this->swizzle = BRW_SWIZZLE_XYZW;
80 this->swizzle = brw_swizzle_for_mask(reg.writemask);
137 this->writemask = brw_mask_for_swizzle(reg.swizzle);
499 /* Replaces unused channels of a swizzle with channels that are used.
524 unsigned swizzle;
533 swizzle = brw_swizzle_for_size(4);
536 swizzle = brw_swizzle_for_size(3);
539 swizzle = brw_swizzle_for_size(2);
550 swizzle = brw_swizzle_for_size(4);
554 swizzle = brw_swizzle_for_mask(inst->dst.writemask);
566 brw_compose_swizzle(swizzle, inst->src[i].swizzle);
567 if (inst->src[i].swizzle != new_swizzle) {
568 inst->src[i].swizzle = new_swizzle;
849 int swizzle,
855 if (devinfo->ver == 6 && is_math() && swizzle != BRW_SWIZZLE_XYZW)
858 /* If we write to the flag register changing the swizzle would change
864 /* We can't swizzle implicit accumulator access. We'd have to
874 /* If this instruction sets anything not referenced by swizzle, then we'd
892 * For any channels in the swizzle's source that were populated by this
896 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
899 vec4_instruction::reswizzle(int dst_writemask, int swizzle)
901 /* Destination write mask doesn't correspond to source swizzle for the dot
924 src[i] = brw_imm_vf4(imm[BRW_GET_SWZ(swizzle, 0)],
925 imm[BRW_GET_SWZ(swizzle, 1)],
926 imm[BRW_GET_SWZ(swizzle, 2)],
927 imm[BRW_GET_SWZ(swizzle, 3)]);
933 src[i].swizzle = brw_compose_swizzle(swizzle, src[i].swizzle);
937 /* Apply the specified swizzle and writemask to the original mask of
941 brw_apply_swizzle_to_mask(swizzle, dst.writemask);
978 if (BRW_GET_SWZ(inst->src[0].swizzle, c) != c) {
1005 brw_apply_inv_swizzle_to_mask(inst->src[0].swizzle,
1070 /* If we can't handle the swizzle, bail. */
1072 inst->src[0].swizzle,
1151 inst->src[0].swizzle);
1482 fprintf(file, "%s", chans[BRW_GET_SWZ(inst->src[i].swizzle, c)]);
1518 reg.swizzle = inst->src[i].swizzle;
1795 * but don't actually use swizzles. Convert swizzle into subnr.
1802 assert(brw_is_single_value_swizzle(inst->src[i].swizzle));
1803 inst->src[i].subnr += 4 * BRW_GET_SWZ(inst->src[i].swizzle, 0);
2079 switch (inst->src[arg].swizzle) {
2096 * but it also means that the swizzle we apply on the first two components of a
2097 * dvec4 is coupled with the swizzle we use for the last 2. In other words,
2098 * only some specific swizzle combinations can be natively supported.
2100 * FIXME: we can go an step further and implement even more swizzle
2121 (brw_mask_for_swizzle(src.swizzle) & 12))
2124 switch (src.swizzle) {
2186 unsigned swz = BRW_GET_SWZ(inst->src[i].swizzle, chan);
2187 scalar_inst->src[i].swizzle = BRW_SWIZZLE4(swz, swz, swz, swz);
2253 /* The align16 hardware can only do 32-bit swizzle channels, so we need to
2254 * translate the logical 64-bit swizzle channels that we use in the Vec4 IR
2255 * to 32-bit swizzle channels in hardware registers.
2258 * translate the swizzle for and @hw_reg is the hardware register where we
2259 * will write the hardware swizzle to use.
2262 * previously so there is just one 64-bit swizzle channel to deal with for any
2278 hw_reg->swizzle = reg.swizzle;
2282 /* Take the 64-bit logical swizzle channel and translate it to 32-bit */
2283 assert(brw_is_single_value_swizzle(reg.swizzle) ||
2287 * HW can only do 32-bit swizzle channels.
2295 * of the original 64-bit swizzle with 2-wide row regioning.
2297 unsigned swizzle0 = BRW_GET_SWZ(reg.swizzle, 0);
2298 unsigned swizzle1 = BRW_GET_SWZ(reg.swizzle, 1);
2299 hw_reg->swizzle = BRW_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1,
2304 * 1. An unsupported swizzle, which should be single-value thanks to the
2307 * 2. A gfx7 supported swizzle. These can be single-value or double-value
2311 unsigned swizzle0 = BRW_GET_SWZ(reg.swizzle, 0);
2312 unsigned swizzle1 = BRW_GET_SWZ(reg.swizzle, 1);
2316 * of the register and then use a X/Y swizzle to select Z/W respectively.
2340 hw_reg->swizzle = BRW_SWIZZLE4(swizzle0 * 2, swizzle0 * 2 + 1,
2362 mask.swizzle = BRW_SWIZZLE4((mask_param + 0) % 4,
2487 * messages that can produce unsupported 64-bit swizzle regions.
2510 * messages that can produce unsupported 64-bit swizzle regions.