Lines Matching defs:swizzle
132 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]),
133 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp])
179 mir_pack_swizzle_64(unsigned *swizzle, unsigned max_component)
184 assert(swizzle[i] <= max_component);
186 unsigned a = (swizzle[i] & 1) ?
226 mir_pack_swizzle(unsigned mask, unsigned *swizzle,
240 packed = mir_pack_swizzle_64(swizzle, components);
243 bool lo = swizzle[0] >= COMPONENT_Z;
244 bool hi = swizzle[1] >= COMPONENT_Z;
264 unreachable("Cannot encode 8/16 swizzle in 64-bit");
267 /* For 32-bit, swizzle packing is stupid-simple. For 16-bit,
274 bool upper = swizzle[first] > 3;
282 unsigned v = swizzle[c];
348 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i],
355 .swizzle = swizzle
377 unsigned v = ins->swizzle[0][c];
384 ins->load_store.swizzle |= (v / step) << (2 * (c / step));
386 ins->load_store.swizzle |= ((v / step) << (4 * c)) |
400 unsigned v = ins->swizzle[i][c];
409 ins->texture.swizzle = packed;
605 ldst.swizzle = 0;
606 ldst.swizzle |= ins->swizzle[3][0] & 3;
607 ldst.swizzle |= (SSA_REG_FROM_FIXED(ins->src[3]) & 1 ? 1 : 0) << 2;
613 ldst.arg_comp = midgard_ldst_comp(ldst.arg_reg, ins->swizzle[1][0], sz);
619 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz);
641 .component = ins->swizzle[2][0]
649 unsigned x = ins->swizzle[3][0];
661 (x << 3) | /* swizzle */
662 (y << 5) | /* swizzle */
663 (z << 7); /* swizzle */
979 /* Atomic ops don't use this swizzle the same way as other ops */