| /third_party/mesa3d/src/nouveau/codegen/ |
| H A D | nv50_ir_emit_nv50.cpp | 841 CodeEmitterNV50::emitQUADOP(const Instruction *i, uint8_t lane, uint8_t quOp) in emitQUADOP() argument
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| /third_party/vixl/test/aarch64/ |
| H A D | test-utils-aarch64.cc | 358 EqualSVELane(uint64_t expected, const RegisterDump* core, const ZRegister& reg, int lane) EqualSVELane() argument
387 EqualSVELane(uint64_t expected, const RegisterDump* core, const PRegister& reg, int lane) EqualSVELane() argument
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| /third_party/python/Objects/ |
| H A D | tupleobject.c | 328 Py_uhash_t lane = PyObject_Hash(item[i]); in tuplehash() local
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| /third_party/skia/include/private/ |
| H A D | SkVx.h | 572 auto lane = [&](size_t i) variable
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| /device/soc/rockchip/common/vendor/drivers/media/platform/rockchip/isp/ |
| H A D | rkisp.c | 1504 u32 ret = 0, val, lane, data;
in rkisp_config_lvds() local
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| /device/soc/rockchip/common/vendor/drivers/phy/ |
| H A D | phy-rockchip-csi2-dphy-hw.c | 290 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane)
in csi_mipidphy_wr_ths_settle() argument
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| H A D | phy-rockchip-mipi-rx.c | 631 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane)
in csi_mipidphy_wr_ths_settle() argument
[all...] |
| /device/soc/rockchip/rk3588/kernel/drivers/media/platform/rockchip/isp/ |
| H A D | rkisp.c | 1542 u32 ret = 0, val, lane, data; in rkisp_config_lvds() local
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| /device/soc/rockchip/rk3588/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-samsung-hdptx.c | 487 rockchip_hdptx_phy_set_voltage(struct rockchip_hdptx_phy *hdptx, struct phy_configure_opts_dp *dp, u8 lane) rockchip_hdptx_phy_set_voltage() argument
581 u8 lane; rockchip_hdptx_phy_set_voltages() local
967 u32 lane; rockchip_hdptx_phy_reset() local
1004 u32 lane; rockchip_hdptx_phy_power_on() local
[all...] |
| H A D | phy-rockchip-csi2-dphy-hw.c | 293 csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw, int hsfreq, enum csi2_dphy_lane lane) csi_mipidphy_wr_ths_settle() argument
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| H A D | phy-rockchip-mipi-rx.c | 655 csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane) csi_mipidphy_wr_ths_settle() argument
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/mips64/ |
| H A D | code-generator-mips64.cc | 3426 unsigned lane = shuffle & 0xFF; in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/compiler/backend/ia32/ |
| H A D | code-generator-ia32.cc | 1975 int8_t lane = i.InputInt8(1); in AssembleArchInstruction() local
3056 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3068 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3171 uint8_t lane in AssembleArchInstruction() local
3186 uint8_t lane = i.InputUint8(1) & 0xf; AssembleArchInstruction() local
[all...] |
| /third_party/node/deps/v8/src/compiler/backend/mips/ |
| H A D | code-generator-mips.cc | 3256 unsigned lane = shuffle & 0xFF; in AssembleArchInstruction() local
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | macro-assembler-arm64.h | 1209 void St1(const VRegister& vt, int lane, const MemOperand& dst) { in St1() argument
1650 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1() argument
1662 void Ld2(const VRegister& vt, const VRegister& vt2, int lane, in Ld2() argument
1676 Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& src) Ld3() argument
1691 Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& src) Ld4() argument
1715 St2(const VRegister& vt, const VRegister& vt2, int lane, const MemOperand& dst) St2() argument
1720 St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, int lane, const MemOperand& dst) St3() argument
1725 St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, const VRegister& vt4, int lane, const MemOperand& dst) St4() argument
[all...] |
| /third_party/node/deps/v8/src/execution/ppc/ |
| H A D | simulator-ppc.h | 421 T get_simd_register_by_lane(int reg, int lane, in get_simd_register_by_lane() argument
444 set_simd_register_by_lane(int reg, int lane, const T& value, bool force_ibm_lane_numbering = true) set_simd_register_by_lane() argument
[all...] |
| /third_party/skia/src/core/ |
| H A D | SkVM.cpp | 719 I32 Builder::load64(Ptr ptr, int lane) { in load64() argument
722 I32 Builder::load128(Ptr ptr, int lane) { in load128() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/s390/ |
| H A D | liftoff-assembler-s390.h | 2667 StoreLane(Register dst, Register offset, uintptr_t offset_imm, LiftoffRegister src, StoreType type, uint8_t lane, uint32_t* protected_store_pc) StoreLane() argument
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| /third_party/node/deps/v8/src/compiler/backend/arm/ |
| H A D | instruction-selector-arm.cc | 2854 InstructionOperand lane = g.UseImmediate(OpParameter<int32_t>(node->op())); in VisitI64x2ReplaceLaneI32Pair() local
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| /third_party/node/deps/v8/src/compiler/backend/x64/ |
| H A D | code-generator-x64.cc | 3842 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3858 uint8_t lane = lanes >> k; in AssembleArchInstruction() local
3930 uint8_t lane = i.InputUint8(index + 1); in AssembleArchInstruction() local
3938 uint8_t lane in AssembleArchInstruction() local
4006 uint8_t lane = i.InputInt8(1) & 0x7; AssembleArchInstruction() local
4020 uint8_t lane = i.InputInt8(1) & 0xf; AssembleArchInstruction() local
[all...] |
| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 503 void Insert(int lane, T new_value) { in Insert() argument
564 WriteLane(T src, int lane) WriteLane() argument
580 WriteLane(vixl::internal::SimFloat16 src, int lane) WriteLane() argument
581 WriteLane(Float16ToRawbits(src), lane); WriteLane() local
647 SetChunk(int lane, ChunkType new_value) SetChunk() argument
667 SetActiveMask(int lane, T new_value) SetActiveMask() argument
1083 GetElementAddress(int lane, int reg) const GetElementAddress() argument
[all...] |
| /device/soc/hisilicon/hi3516dv300/sdk_linux/drv/interdrv/hi3516cv500/mipi_rx/ |
| H A D | mipi_rx_hal.c | 1663 short get_sensor_lane_index(short lane, const short lane_id[LVDS_LANE_NUM]) in get_sensor_lane_index() argument
1688 short lane; in mipi_rx_drv_set_lvds_phy_sync_code() local
2036 mipi_rx_drv_get_lvds_lane_imgsize_statis(combo_dev_t devno, short lane, img_size_t *p_size) mipi_rx_drv_get_lvds_lane_imgsize_statis() argument
[all...] |
| /device/soc/hisilicon/common/platform/mipi_csi/ |
| H A D | mipi_rx_hi2121.c | 1658 short GetSensorLaneIndex(short lane, const short laneId[LVDS_LANE_NUM]) in GetSensorLaneIndex() argument
1681 short lane; in MipiRxDrvSetLvdsPhySyncCode() local
2029 MipiRxDrvGetLvdsLaneImgsizeStatis(uint8_t devno, short lane, ImgSize *pSize) MipiRxDrvGetLvdsLaneImgsizeStatis() argument
[all...] |
| /device/soc/rockchip/common/sdk_linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-typec.c | 716 static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
in tcphy_tx_usb3_cfg_lane() argument
726 static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
in tcphy_rx_usb3_cfg_lane() argument
740 tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate, u8 swing, u8 pre_emp, u32 lane) tcphy_dp_cfg_lane() argument
[all...] |
| /third_party/node/deps/v8/src/wasm/baseline/ppc/ |
| H A D | liftoff-assembler-ppc.h | 1763 StoreLane(Register dst, Register offset, uintptr_t offset_imm, LiftoffRegister src, StoreType type, uint8_t lane, uint32_t* protected_store_pc) StoreLane() argument
|