Lines Matching defs:lane
2382 void Assembler::ld2(const VRegister& vt, const VRegister& vt2, int lane,
2387 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad2);
2408 const VRegister& vt3, int lane, const MemOperand& src) {
2413 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad3);
2437 const VRegister& vt3, const VRegister& vt4, int lane,
2444 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad4);
2498 void Assembler::st2(const VRegister& vt, const VRegister& vt2, int lane,
2503 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore2);
2516 const VRegister& vt3, int lane, const MemOperand& dst) {
2521 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore3);
2536 const VRegister& vt3, const VRegister& vt4, int lane,
2543 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore4);
2546 void Assembler::LoadStoreStructSingle(const VRegister& vt, uint32_t lane,
2554 DCHECK_LT(lane, kQRegSize / lane_size);
2558 lane *= lane_size;
2561 // significant bit of the size field, so we increment lane here to account for
2563 if (lane_size == 8) lane++;
2565 Instr size = (lane << NEONLSSize_offset) & NEONLSSize_mask;
2566 Instr s = (lane << (NEONS_offset - 2)) & NEONS_mask;
2567 Instr q = (lane << (NEONQ_offset - 3)) & NEONQ_mask;
2588 void Assembler::ld1(const VRegister& vt, int lane, const MemOperand& src) {
2589 LoadStoreStructSingle(vt, lane, src, NEONLoadStoreSingleStructLoad1);
2596 void Assembler::st1(const VRegister& vt, int lane, const MemOperand& dst) {
2597 LoadStoreStructSingle(vt, lane, dst, NEONLoadStoreSingleStructStore1);