Lines Matching defs:lane
499 // unchanged. The lane parameter indicates where in the register the value
503 void Insert(int lane, T new_value) {
504 WriteLane(new_value, lane);
514 // Get the lane value as the specified type. The value is truncated if
517 T GetLane(int lane) const {
519 ReadLane(&result, lane);
523 VIXL_DEPRECATED("GetLane", T Get(int lane) const) {
524 return GetLane(lane);
528 // lane 0.
557 void ReadLane(T* dst, int lane) const {
558 VIXL_ASSERT(lane >= 0);
559 VIXL_ASSERT((sizeof(*dst) + (lane * sizeof(*dst))) <= GetSizeInBytes());
560 memcpy(dst, &value_[lane * sizeof(*dst)], sizeof(*dst));
564 void WriteLane(T src, int lane) {
565 VIXL_ASSERT(lane >= 0);
566 VIXL_ASSERT((sizeof(src) + (lane * sizeof(src))) <= GetSizeInBytes());
567 memcpy(&value_[lane * sizeof(src)], &src, sizeof(src));
574 void ReadLane(vixl::internal::SimFloat16* dst, int lane) const {
576 ReadLane(&rawbits, lane);
580 void WriteLane(vixl::internal::SimFloat16 src, int lane) {
581 WriteLane(Float16ToRawbits(src), lane);
619 // Assign a bit into the end positon of the specified lane.
645 ChunkType GetChunk(int lane) const { return GetActiveMask<ChunkType>(lane); }
647 void SetChunk(int lane, ChunkType new_value) {
648 SetActiveMask(lane, new_value);
654 for (int lane = 0;
655 lane < (static_cast<int>(register_.GetSizeInBits() / chunk_size));
656 lane++) {
657 SetChunk(lane, bits);
662 T GetActiveMask(int lane) const {
663 return register_.GetLane<T>(lane);
667 void SetActiveMask(int lane, T new_value) {
668 register_.Insert<T>(lane, new_value);
707 // and additional information to represent lane state.
871 // Saturation state for each lane of a vector.
995 // Allocate one saturation state entry per lane; largest register is type Q,
999 // Allocate one rounding state entry per lane.
1003 // Represent an SVE addressing mode and abstract per-lane address generation to
1007 // occupied by each lane (`SetMsizeInBytesLog2()`) and the number of elements in
1049 // Set `msize` -- the memory occupied by each lane -- for address
1083 uint64_t GetElementAddress(int lane, int reg) const {
1087 return GetStructAddress(lane) + (reg * GetMsizeInBytes());
1091 uint64_t GetStructAddress(int lane) const;
2158 // The lane size.
2262 // Keep the FP and lane size fields.
2269 // combination of FP and lane size that SVE formats do.
2516 // know the lane type, so there's no need to accept a `format`.
2581 // know the lane type, so these don't accept a `format`.
2591 // Single-structure (single-lane) accesses.
2594 int lane,
2641 // lane size is not respected when interpreting lane_mask: unaligned bits
2651 // If a lane is active in both `access_mask` and `future_access_mask`,
3430 // Add `value` to each lane of `src1`, treating `value` as unsigned for the
3593 // Subtract `value` from each lane of `src1`, treating `value` as unsigned for
3850 // if any predicate lane is active, false otherwise. The second part takes the
3851 // value of the last active (plus offset) lane, or last (plus offset) lane if
4971 // Store each active zt<i>[lane] to `addr.GetElementAddress(lane, ...)`.
4981 // Load each active zt<i>[lane] from `addr.GetElementAddress(lane, ...)`.
4990 // fails, the corresponding lane and all subsequent lanes are filled with
5001 // generate a real fault if it is inaccessible. If the lane is not active in
5051 // Return the first or last active lane, or -1 if none are active.
5238 // Construct a SimVRegister from a SimPRegister, where each byte-sized lane of
5243 // Set each predicate flag in pd where the corresponding assigned-sized lane
5245 // operation to ExpandToSimVRegister(), except that any non-zero lane is