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Searched defs:devinfo (Results 176 - 200 of 272) sorted by relevance

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/third_party/NuttX/drivers/usbdev/gadget/
H A Drndis.c1672 struct usbdev_devinfo_s *devinfo; in usbclass_bind() local
2347 rndis_classobject(int minor, struct usbdev_devinfo_s *devinfo, struct usbdevclass_driver_s **devclass_drvr) rndis_classobject() argument
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/third_party/mesa3d/src/broadcom/qpu/
H A Dqpu_pack.c217 v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo, in v3d_qpu_sig_unpack() argument
237 v3d_qpu_sig_pack(const struct v3d_device_info *devinfo, in v3d_qpu_sig_pack() argument
288 v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo, in v3d_qpu_small_imm_unpack() argument
300 v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo, in v3d_qpu_small_imm_pack() argument
317 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo, in v3d_qpu_flags_unpack() argument
366 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo, in v3d_qpu_flags_pack() argument
591 opcode_invalid_in_version(const struct v3d_device_info *devinfo, const struct opcode_desc *op_desc) opcode_invalid_in_version() argument
599 lookup_opcode_from_packed(const struct v3d_device_info *devinfo, const struct opcode_desc *opcodes, size_t num_opcodes, uint32_t opcode, uint32_t mux_a, uint32_t mux_b) lookup_opcode_from_packed() argument
740 v3d_qpu_add_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst, struct v3d_qpu_instr *instr) v3d_qpu_add_unpack() argument
895 v3d_qpu_mul_unpack(const struct v3d_device_info *devinfo, uint64_t packed_inst, struct v3d_qpu_instr *instr) v3d_qpu_mul_unpack() argument
968 lookup_opcode_from_instr(const struct v3d_device_info *devinfo, const struct opcode_desc *opcodes, size_t num_opcodes, uint8_t op) lookup_opcode_from_instr() argument
988 v3d_qpu_add_pack(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *instr, uint64_t *packed_instr) v3d_qpu_add_pack() argument
1201 v3d_qpu_mul_pack(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *instr, uint64_t *packed_instr) v3d_qpu_mul_pack() argument
1308 v3d_qpu_instr_unpack_alu(const struct v3d_device_info *devinfo, uint64_t packed_instr, struct v3d_qpu_instr *instr) v3d_qpu_instr_unpack_alu() argument
1348 v3d_qpu_instr_unpack_branch(const struct v3d_device_info *devinfo, uint64_t packed_instr, struct v3d_qpu_instr *instr) v3d_qpu_instr_unpack_branch() argument
1393 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo, uint64_t packed_instr, struct v3d_qpu_instr *instr) v3d_qpu_instr_unpack() argument
1412 v3d_qpu_instr_pack_alu(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *instr, uint64_t *packed_instr) v3d_qpu_instr_pack_alu() argument
1459 v3d_qpu_instr_pack_branch(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *instr, uint64_t *packed_instr) v3d_qpu_instr_pack_branch() argument
1510 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo, const struct v3d_qpu_instr *instr, uint64_t *packed_instr) v3d_qpu_instr_pack() argument
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/third_party/mesa3d/src/broadcom/compiler/
H A Dvir_register_allocate.c91 qinst_writes_tmu(const struct v3d_device_info *devinfo, in qinst_writes_tmu() argument
100 is_end_of_tmu_sequence(const struct v3d_device_info *devinfo, in is_end_of_tmu_sequence() argument
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/third_party/mesa3d/src/intel/common/
H A Dintel_decoder.c591 intel_spec_load(const struct intel_device_info *devinfo) in intel_spec_load() argument
731 intel_spec_load_from_path(const struct intel_device_info *devinfo, in intel_spec_load_from_path() argument
/third_party/mesa3d/src/intel/compiler/
H A Dbrw_fs_generator.cpp58 brw_reg_from_fs_reg(const struct intel_device_info *devinfo, fs_inst *inst, in brw_reg_from_fs_reg() argument
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H A Dbrw_lower_logical_sends.cpp36 const intel_device_info *devinfo = bld.shader->devinfo; in lower_urb_read_logical_send() local
81 const intel_device_info *devinfo = bld.shader->devinfo; in lower_urb_write_logical_send() local
157 const intel_device_info *devinfo = bld.shader->devinfo; in lower_fb_write_logical_send() local
415 const intel_device_info *devinfo = bld.shader->devinfo; lower_fb_read_logical_send() local
671 is_high_sampler(const struct intel_device_info *devinfo, const fs_reg &sampler) is_high_sampler() argument
680 sampler_msg_type(const intel_device_info *devinfo, opcode opcode, bool shadow_compare) sampler_msg_type() argument
799 const intel_device_info *devinfo = bld.shader->devinfo; lower_sampler_logical_send_gfx7() local
1188 get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, opcode op, const fs_reg *src) get_sampler_msg_payload_type_bit_size() argument
1245 const intel_device_info *devinfo = bld.shader->devinfo; lower_sampler_logical_send() local
1329 const ASSERTED intel_device_info *devinfo = bld.shader->devinfo; setup_surface_descriptors() local
1361 const intel_device_info *devinfo = bld.shader->devinfo; lower_surface_logical_send() local
1674 const intel_device_info *devinfo = bld.shader->devinfo; lower_lsc_surface_logical_send() local
1835 const intel_device_info *devinfo = bld.shader->devinfo; lower_surface_block_logical_send() local
1951 const intel_device_info *devinfo = bld.shader->devinfo; lower_lsc_a64_logical_send() local
2061 const intel_device_info *devinfo = bld.shader->devinfo; lower_a64_logical_send() local
2218 const intel_device_info *devinfo = bld.shader->devinfo; lower_lsc_varying_pull_constant_logical_send() local
2296 const intel_device_info *devinfo = bld.shader->devinfo; lower_varying_pull_constant_logical_send() local
2418 const intel_device_info *devinfo = bld.shader->devinfo; lower_btd_logical_send() local
2488 const intel_device_info *devinfo = bld.shader->devinfo; lower_trace_ray_logical_send() local
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H A Dbrw_nir.c649 const struct intel_device_info *devinfo = compiler->devinfo; in lower_bit_size_callback() local
815 const struct intel_device_info *devinfo = compiler->devinfo; in brw_preprocess_nir() local
416 brw_nir_lower_fs_inputs(nir_shader *nir, const struct intel_device_info *devinfo, const struct brw_wm_prog_key *key) brw_nir_lower_fs_inputs() argument
1088 const struct intel_device_info *devinfo = compiler->devinfo; brw_vectorize_lower_mem_access() local
1145 const struct intel_device_info *devinfo = compiler->devinfo; brw_postprocess_nir() local
1328 const struct intel_device_info *devinfo = compiler->devinfo; brw_nir_apply_sampler_key() local
1558 brw_type_for_nir_type(const struct intel_device_info *devinfo, nir_alu_type type) brw_type_for_nir_type() argument
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H A Dbrw_vec4.cpp237 vec4_instruction::can_do_source_mods(const struct intel_device_info *devinfo) in can_do_source_mods() argument
272 vec4_instruction::can_do_writemask(const struct intel_device_info *devinfo) in can_do_writemask() argument
847 vec4_instruction::can_reswizzle(const struct intel_device_info *devinfo, in can_reswizzle() argument
1866 get_lowered_simd_width(const struct intel_device_info *devinfo, enum shader_dispatch_mode dispatch_mode, unsigned stage, const vec4_instruction *inst) get_lowered_simd_width() argument
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H A Dbrw_nir_rt_builder.h76 brw_nir_rt_load_num_simd_lanes_per_dss(nir_builder *b, const struct intel_device_info *devinfo) brw_nir_rt_load_num_simd_lanes_per_dss() argument
162 brw_nir_num_rt_stacks(nir_builder *b, const struct intel_device_info *devinfo) brw_nir_num_rt_stacks() argument
170 brw_nir_rt_sw_hotzone_addr(nir_builder *b, const struct intel_device_info *devinfo) brw_nir_rt_sw_hotzone_addr() argument
186 brw_nir_rt_sync_stack_addr(nir_builder *b, nir_ssa_def *base_mem_addr, const struct intel_device_info *devinfo) brw_nir_rt_sync_stack_addr() argument
271 brw_nir_rt_sw_stack_addr(nir_builder *b, const struct intel_device_info *devinfo) brw_nir_rt_sw_stack_addr() argument
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H A Dbrw_vec4_nir.cpp285 const intel_device_info *devinfo = bld.shader->devinfo; in setup_imm_df() local
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H A Dbrw_vec4_visitor.cpp923 assert(varying < VARYING_SLOT_MAX); unsigned num_comps = output_num_components[varying][component]; if (num_comps == 0) return NULL; assert(output_reg[varying][component].type == reg.type); current_annotation = output_reg_annotation[varying]; if (output_reg[varying][component].file != BAD_FILE) { src_reg src = src_reg(output_reg[varying][component]); src.swizzle = BRW_SWZ_COMP_OUTPUT(component); reg.writemask = brw_writemask_for_component_packing(num_comps, component); return emit(MOV(reg, src)); } return NULL; } void vec4_visitor::emit_urb_slot(dst_reg reg, int varying) { reg.type = BRW_REGISTER_TYPE_F; output_reg[varying][0].type = reg.type; switch (varying) { case VARYING_SLOT_PSIZ: { current_annotation = �; emit_psiz_and_flags(reg); break; } case BRW_VARYING_SLOT_NDC: current_annotation = �; if (output_reg[BRW_VARYING_SLOT_NDC][0].file != BAD_FILE) emit(MOV(reg, src_reg(output_reg[BRW_VARYING_SLOT_NDC][0]))); break; case VARYING_SLOT_POS: current_annotation = �; if (output_reg[VARYING_SLOT_POS][0].file != BAD_FILE) emit(MOV(reg, src_reg(output_reg[VARYING_SLOT_POS][0]))); break; case BRW_VARYING_SLOT_PAD: break; default: for (int i = 0; i < 4; i++) { emit_generic_urb_slot(reg, varying, i); } break; } } static unsigned align_interleaved_urb_mlen(const struct intel_device_info *devinfo, unsigned mlen) { if (devinfo->ver >= 6) emit_generic_urb_slot() argument
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H A Dbrw_vec4_generator.cpp117 const struct intel_device_info *devinfo = p->devinfo; in generate_tex() local
733 const struct intel_device_info *devinfo = p->devinfo; generate_tcs_get_instance_id() local
765 const struct intel_device_info *devinfo = p->devinfo; generate_tcs_urb_write() local
949 const struct intel_device_info *devinfo = p->devinfo; generate_vec4_urb_read() local
974 const struct intel_device_info *devinfo = p->devinfo; generate_tcs_release_input() local
1054 const struct intel_device_info *devinfo = p->devinfo; generate_tcs_create_barrier_header() local
1144 const struct intel_device_info *devinfo = p->devinfo; generate_scratch_read() local
1190 const struct intel_device_info *devinfo = p->devinfo; generate_scratch_write() local
1267 const struct intel_device_info *devinfo = p->devinfo; generate_pull_constant_load() local
1353 const struct intel_device_info *devinfo = p->devinfo; generate_pull_constant_load_gfx7() local
1524 const struct intel_device_info *devinfo = p->devinfo; generate_code() local
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/third_party/mesa3d/src/intel/blorp/
H A Dblorp_genX_exec.h897 const struct intel_device_info *devinfo = batch->blorp->compiler->devinfo; in blorp_emit_ps_config() local
2143 const struct intel_device_info *devinfo = batch->blorp->compiler->devinfo; in blorp_exec_compute() local
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H A Dblorp_clear.c903 blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo, in blorp_can_hiz_clear_depth() argument
/third_party/mesa3d/src/intel/perf/
H A Dintel_perf.c350 const struct intel_device_info *devinfo = &perf->devinfo; in compute_topology_builtins() local
174 register_oa_config(struct intel_perf_config *perf, const struct intel_device_info *devinfo, const struct intel_perf_query_info *query, uint64_t config_id) register_oa_config() argument
189 enumerate_sysfs_metrics(struct intel_perf_config *perf, const struct intel_device_info *devinfo) enumerate_sysfs_metrics() argument
235 add_all_metrics(struct intel_perf_config *perf, const struct intel_device_info *devinfo) add_all_metrics() argument
322 init_oa_configs(struct intel_perf_config *perf, int fd, const struct intel_device_info *devinfo) init_oa_configs() argument
427 get_register_queries_function(const struct intel_device_info *devinfo) get_register_queries_function() argument
498 load_pipeline_statistic_metrics(struct intel_perf_config *perf_cfg, const struct intel_device_info *devinfo) load_pipeline_statistic_metrics() argument
705 oa_metrics_available(struct intel_perf_config *perf, int fd, const struct intel_device_info *devinfo, bool use_register_snapshots) oa_metrics_available() argument
756 load_oa_metrics(struct intel_perf_config *perf, int fd, const struct intel_device_info *devinfo) load_oa_metrics() argument
1018 intel_perf_query_result_read_frequencies(struct intel_perf_query_result *result, const struct intel_device_info *devinfo, const uint32_t *start, const uint32_t *end) intel_perf_query_result_read_frequencies() argument
1043 can_use_mi_rpc_bc_counters(const struct intel_device_info *devinfo) can_use_mi_rpc_bc_counters() argument
1127 intel_perf_query_result_read_gt_frequency(struct intel_perf_query_result *result, const struct intel_device_info *devinfo, const uint32_t start, const uint32_t end) intel_perf_query_result_read_gt_frequency() argument
1197 const struct intel_device_info *devinfo = &query->perf->devinfo; intel_perf_query_result_accumulate_fields() local
1318 intel_perf_init_query_fields(struct intel_perf_config *perf_cfg, const struct intel_device_info *devinfo, bool use_register_snapshots) intel_perf_init_query_fields() argument
1403 intel_perf_init_metrics(struct intel_perf_config *perf_cfg, const struct intel_device_info *devinfo, int drm_fd, bool include_pipeline_statistics, bool use_register_snapshots) intel_perf_init_metrics() argument
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H A Dintel_perf_query.c247 const struct intel_device_info *devinfo; member
1238 oa_report_ctx_id_valid(const struct intel_device_info *devinfo, in oa_report_ctx_id_valid() argument
586 intel_perf_init_context(struct intel_perf_context *perf_ctx, struct intel_perf_config *perf_cfg, void * mem_ctx, void * ctx, void * bufmgr, const struct intel_device_info *devinfo, uint32_t hw_ctx, int drm_fd) intel_perf_init_context() argument
1269 const struct intel_device_info *devinfo = perf_ctx->devinfo; accumulate_oa_reports() local
1597 const struct intel_device_info *devinfo = perf_ctx->devinfo; intel_perf_get_query_data() local
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/third_party/mesa3d/src/intel/dev/
H A Dintel_device_info.c1097 reset_masks(struct intel_device_info *devinfo) in reset_masks() argument
1113 update_slice_subslice_counts(struct intel_device_info *devinfo) update_slice_subslice_counts() argument
1132 update_pixel_pipes(struct intel_device_info *devinfo, uint8_t *subslice_masks) update_pixel_pipes() argument
1168 update_l3_banks(struct intel_device_info *devinfo) update_l3_banks() argument
1205 update_from_single_slice_topology(struct intel_device_info *devinfo, const struct drm_i915_query_topology_info *topology, const struct drm_i915_query_topology_info *geom_topology) update_from_single_slice_topology() argument
1284 update_from_topology(struct intel_device_info *devinfo, const struct drm_i915_query_topology_info *topology) update_from_topology() argument
1325 update_from_masks(struct intel_device_info *devinfo, uint32_t slice_mask, uint32_t subslice_mask, uint32_t n_eus) update_from_masks() argument
1387 fill_masks(struct intel_device_info *devinfo) fill_masks() argument
1437 update_cs_workgroup_threads(struct intel_device_info *devinfo) update_cs_workgroup_threads() argument
1452 intel_get_device_info_from_pci_id(int pci_id, struct intel_device_info *devinfo) intel_get_device_info_from_pci_id() argument
1538 getparam_topology(struct intel_device_info *devinfo, int fd) getparam_topology() argument
1568 query_topology(struct intel_device_info *devinfo, int fd) query_topology() argument
1600 query_regions(struct intel_device_info *devinfo, int fd, bool update) query_regions() argument
1678 compute_system_memory(struct intel_device_info *devinfo, bool update) compute_system_memory() argument
1792 fixup_chv_device_info(struct intel_device_info *devinfo) fixup_chv_device_info() argument
1834 init_max_scratch_ids(struct intel_device_info *devinfo) init_max_scratch_ids() argument
1938 intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo) intel_get_device_info_from_fd() argument
2055 intel_device_info_update_memory_info(struct intel_device_info *devinfo, int fd) intel_device_info_update_memory_info() argument
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H A Dintel_device_info.h437 intel_device_info_slice_available(const struct intel_device_info *devinfo, in intel_device_info_slice_available() argument
445 intel_device_info_subslice_available(const struct intel_device_info *devinfo, int slice, int subslice) intel_device_info_subslice_available() argument
453 intel_device_info_eu_available(const struct intel_device_info *devinfo, int slice, int subslice, int eu) intel_device_info_eu_available() argument
463 intel_device_info_subslice_total(const struct intel_device_info *devinfo) intel_device_info_subslice_total() argument
475 intel_device_info_eu_total(const struct intel_device_info *devinfo) intel_device_info_eu_total() argument
486 intel_device_info_num_dual_subslices(UNUSED const struct intel_device_info *devinfo) intel_device_info_num_dual_subslices() argument
495 intel_device_info_timebase_scale(const struct intel_device_info *devinfo, uint64_t gpu_timestamp) intel_device_info_timebase_scale() argument
507 intel_vram_all_mappable(const struct intel_device_info *devinfo) intel_vram_all_mappable() argument
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/third_party/mesa3d/src/intel/vulkan/
H A Danv_cmd_buffer.c243 const struct intel_device_info *devinfo = &cmd_buffer->device->info; in anv_cmd_buffer_emit_state_base_address() local
256 const struct intel_device_info *devinfo = &cmd_buffer->device->info; in anv_cmd_buffer_mark_image_written() local
266 const struct intel_device_info *devinfo = &cmd_buffer->device->info; in anv_cmd_emit_conditional_render_predicate() local
739 const struct intel_device_info *devinfo = &cmd_buffer->device->info; in anv_cmd_buffer_cs_push_constants() local
H A DgenX_pipeline.c276 const struct intel_device_info *devinfo = &device->info; in emit_urb_setup() local
325 const struct intel_device_info *devinfo = &pipeline->base.device->info; in emit_urb_setup_mesh() local
1021 const struct intel_device_info *devinfo = &pipeline->base.device->info; in emit_cb_state() local
1517 const struct intel_device_info *devinfo = &pipeline->base.device->info; in emit_3dstate_vs() local
1606 const struct intel_device_info *devinfo in emit_3dstate_hs_te_ds() local
1751 const struct intel_device_info *devinfo = &pipeline->base.device->info; emit_3dstate_gs() local
1908 const struct intel_device_info *devinfo = &pipeline->base.device->info; emit_3dstate_wm() local
1918 UNUSED const struct intel_device_info *devinfo = emit_3dstate_ps() local
2186 const struct intel_device_info *devinfo = &pipeline->base.device->info; emit_task_state() local
2243 const struct intel_device_info *devinfo = &pipeline->base.device->info; emit_mesh_state() local
2392 const struct intel_device_info *devinfo = &device->info; compute_pipeline_emit() local
2408 const struct intel_device_info *devinfo = &device->info; compute_pipeline_emit() local
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H A Danv_formats.c472 anv_get_format_plane(const struct intel_device_info *devinfo, in anv_get_format_plane() argument
536 anv_get_format_aspect(const struct intel_device_info *devinfo, in anv_get_format_aspect() argument
548 anv_get_image_format_features2(const struct intel_device_info *devinfo, in anv_get_image_format_features2() argument
828 get_buffer_format_features2(const struct intel_device_info *devinfo, VkFormat vk_format, const struct anv_format *anv_format) get_buffer_format_features2() argument
878 const struct intel_device_info *devinfo = &physical_device->info; get_drm_format_modifier_properties_list() local
913 const struct intel_device_info *devinfo = &physical_device->info; get_drm_format_modifier_properties_list_2() local
948 const struct intel_device_info *devinfo = &physical_device->info; anv_GetPhysicalDeviceFormatProperties2() local
1005 const struct intel_device_info *devinfo = &physical_device->info; anv_get_image_format_properties() local
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/third_party/mesa3d/src/intel/tools/
H A Daubinator_viewer_decoder.cpp31 aub_viewer_decode_ctx_init(struct aub_viewer_decode_ctx *ctx, struct aub_viewer_cfg *cfg, struct aub_viewer_decode_cfg *decode_cfg, const struct intel_device_info *devinfo, struct intel_spec *spec, struct intel_batch_decode_bo (*get_bo)(void *, bool, uint64_t), unsigned (*get_state_size)(void *, uint32_t), void *user_data) aub_viewer_decode_ctx_init() argument
H A Daub_write.c464 get_context_init(const struct intel_device_info *devinfo, in get_context_init() argument
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H A Daubinator_error_decode.c164 instdone_register_for_ring(const struct intel_device_info *devinfo, in instdone_register_for_ring() argument
205 print_pgtbl_err(unsigned int reg, struct intel_device_info *devinfo) in print_pgtbl_err() argument
236 print_snb_fence(struct intel_device_info *devinfo, uint64_t fence) in print_snb_fence() argument
247 print_i965_fence(struct intel_device_info *devinfo, uint64_t fence) in print_i965_fence() argument
258 print_fence(struct intel_device_info *devinfo, uint64_t fence) in print_fence() argument
268 print_fault_data(struct intel_device_info *devinfo, uint32_t data1, uint32_t data0) print_fault_data() argument
421 struct intel_device_info devinfo; read_data_file() local
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/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_blit.c241 const struct intel_device_info *devinfo = isl_dev->info; in iris_blorp_surf_for_resource() local
291 const struct intel_device_info *devinfo = &batch->screen->devinfo; in tex_cache_flush_hack() local
368 const struct intel_device_info *devinfo = &screen->devinfo; in iris_blit() local
575 struct intel_device_info *devinfo = &screen->devinfo; get_copy_region_aux_settings() local
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