Lines Matching defs:devinfo

1097 reset_masks(struct intel_device_info *devinfo)
1099 devinfo->subslice_slice_stride = 0;
1100 devinfo->eu_subslice_stride = 0;
1101 devinfo->eu_slice_stride = 0;
1103 devinfo->num_slices = 0;
1104 memset(devinfo->num_subslices, 0, sizeof(devinfo->num_subslices));
1106 memset(&devinfo->slice_masks, 0, sizeof(devinfo->slice_masks));
1107 memset(devinfo->subslice_masks, 0, sizeof(devinfo->subslice_masks));
1108 memset(devinfo->eu_masks, 0, sizeof(devinfo->eu_masks));
1109 memset(devinfo->ppipe_subslices, 0, sizeof(devinfo->ppipe_subslices));
1113 update_slice_subslice_counts(struct intel_device_info *devinfo)
1115 devinfo->num_slices = __builtin_popcount(devinfo->slice_masks);
1116 devinfo->subslice_total = 0;
1117 for (int s = 0; s < devinfo->max_slices; s++) {
1118 if (!intel_device_info_slice_available(devinfo, s))
1121 for (int b = 0; b < devinfo->subslice_slice_stride; b++) {
1122 devinfo->num_subslices[s] +=
1123 __builtin_popcount(devinfo->subslice_masks[s * devinfo->subslice_slice_stride + b]);
1125 devinfo->subslice_total += devinfo->num_subslices[s];
1127 assert(devinfo->num_slices > 0);
1128 assert(devinfo->subslice_total > 0);
1132 update_pixel_pipes(struct intel_device_info *devinfo, uint8_t *subslice_masks)
1134 if (devinfo->ver < 11)
1142 assert(devinfo->slice_masks == 1 || devinfo->verx10 >= 125);
1151 const unsigned ppipe_bits = devinfo->ver >= 12 ? 2 : 4;
1155 devinfo->max_subslices_per_slice * devinfo->subslice_slice_stride;
1157 BITFIELD_RANGE(offset % devinfo->max_subslices_per_slice, ppipe_bits);
1159 if (subslice_idx < ARRAY_SIZE(devinfo->subslice_masks))
1160 devinfo->ppipe_subslices[p] =
1163 devinfo->ppipe_subslices[p] = 0;
1168 update_l3_banks(struct intel_device_info *devinfo)
1170 if (devinfo->ver != 12)
1173 if (devinfo->verx10 >= 125) {
1174 if (devinfo->subslice_total > 16) {
1175 assert(devinfo->subslice_total <= 32);
1176 devinfo->l3_banks = 32;
1177 } else if (devinfo->subslice_total > 8) {
1178 devinfo->l3_banks = 16;
1180 devinfo->l3_banks = 8;
1183 assert(devinfo->num_slices == 1);
1184 if (devinfo->subslice_total >= 6) {
1185 assert(devinfo->subslice_total == 6);
1186 devinfo->l3_banks = 8;
1187 } else if (devinfo->subslice_total > 2) {
1188 devinfo->l3_banks = 6;
1190 devinfo->l3_banks = 4;
1205 update_from_single_slice_topology(struct intel_device_info *devinfo,
1214 uint8_t geom_subslice_masks[ARRAY_SIZE(devinfo->subslice_masks)] = { 0 };
1216 assert(devinfo->verx10 >= 125);
1218 reset_masks(devinfo);
1227 devinfo->max_subslices_per_slice = 4;
1228 devinfo->max_eus_per_subslice = 16;
1229 devinfo->subslice_slice_stride = 1;
1230 devinfo->eu_slice_stride = DIV_ROUND_UP(16 * 4, 8);
1231 devinfo->eu_subslice_stride = DIV_ROUND_UP(16, 8);
1250 geom_subslice_masks[s * devinfo->subslice_slice_stride +
1257 devinfo->max_slices = MAX2(devinfo->max_slices, s + 1);
1258 devinfo->slice_masks |= 1u << s;
1260 devinfo->subslice_masks[s * devinfo->subslice_slice_stride +
1263 for (uint32_t eu = 0; eu < devinfo->max_eus_per_subslice; eu++) {
1272 devinfo->eu_masks[s * devinfo->eu_slice_stride +
1273 ss * devinfo->eu_subslice_stride +
1278 update_slice_subslice_counts(devinfo);
1279 update_pixel_pipes(devinfo, geom_subslice_masks);
1280 update_l3_banks(devinfo);
1284 update_from_topology(struct intel_device_info *devinfo,
1287 reset_masks(devinfo);
1293 devinfo->subslice_slice_stride = topology->subslice_stride;
1295 devinfo->eu_subslice_stride = DIV_ROUND_UP(topology->max_eus_per_subslice, 8);
1296 devinfo->eu_slice_stride = topology->max_subslices * devinfo->eu_subslice_stride;
1298 assert(sizeof(devinfo->slice_masks) >= DIV_ROUND_UP(topology->max_slices, 8));
1299 memcpy(&devinfo->slice_masks, topology->data, DIV_ROUND_UP(topology->max_slices, 8));
1300 devinfo->max_slices = topology->max_slices;
1301 devinfo->max_subslices_per_slice = topology->max_subslices;
1302 devinfo->max_eus_per_subslice = topology->max_eus_per_subslice;
1306 assert(sizeof(devinfo->subslice_masks) >= subslice_mask_len);
1307 memcpy(devinfo->subslice_masks, &topology->data[topology->subslice_offset],
1312 assert(sizeof(devinfo->eu_masks) >= eu_mask_len);
1313 memcpy(devinfo->eu_masks, &topology->data[topology->eu_offset], eu_mask_len);
1316 update_slice_subslice_counts(devinfo);
1317 update_pixel_pipes(devinfo, devinfo->subslice_masks);
1318 update_l3_banks(devinfo);
1325 update_from_masks(struct intel_device_info *devinfo, uint32_t slice_mask,
1379 update_from_topology(devinfo, topology);
1387 fill_masks(struct intel_device_info *devinfo)
1392 for (int s = 1; s < devinfo->num_slices; s++)
1393 assert(devinfo->num_subslices[0] == devinfo->num_subslices[s]);
1395 update_from_masks(devinfo,
1396 (1U << devinfo->num_slices) - 1,
1397 (1U << devinfo->num_subslices[0]) - 1,
1398 devinfo->num_slices * devinfo->num_subslices[0] *
1399 devinfo->max_eus_per_subslice);
1437 update_cs_workgroup_threads(struct intel_device_info *devinfo)
1446 devinfo->max_cs_workgroup_threads =
1447 devinfo->verx10 >= 125 ? devinfo->max_cs_threads :
1448 MIN2(devinfo->max_cs_threads, 64);
1453 struct intel_device_info *devinfo)
1458 case id: *devinfo = intel_device_info_##family; break;
1464 case id: *devinfo = intel_device_info_gfx3; break;
1478 sizeof(devinfo->name)); \
1479 strncpy(devinfo->name, _name " (" _fam_str ")", sizeof(devinfo->name)); \
1484 strncpy(devinfo->name, "Intel Unknown", sizeof(devinfo->name));
1487 fill_masks(devinfo);
1503 switch(devinfo->ver) {
1505 devinfo->max_wm_threads = 64 /* threads-per-PSD */
1506 * devinfo->num_slices
1511 devinfo->max_wm_threads = 128 /* threads-per-PSD */
1512 * devinfo->num_slices
1516 assert(devinfo->ver < 9);
1520 assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
1522 if (devinfo->verx10 == 0)
1523 devinfo->verx10 = devinfo->ver * 10;
1525 if (devinfo->display_ver == 0)
1526 devinfo->display_ver = devinfo->ver;
1528 update_cs_workgroup_threads(devinfo);
1538 getparam_topology(struct intel_device_info *devinfo, int fd)
1552 return update_from_masks(devinfo, slice_mask, subslice_mask, n_eus);
1558 if (devinfo->ver >= 8)
1565 * preferred API for updating the topology in devinfo (kernel 4.17+)
1568 query_topology(struct intel_device_info *devinfo, int fd)
1575 if (devinfo->verx10 >= 125) {
1583 update_from_single_slice_topology(devinfo, topo_info, geom_topo_info);
1586 update_from_topology(devinfo, topo_info);
1600 query_regions(struct intel_device_info *devinfo, int fd, bool update)
1612 devinfo->mem.sram.mem_class = mem->region.memory_class;
1613 devinfo->mem.sram.mem_instance = mem->region.memory_instance;
1614 devinfo->mem.sram.mappable.size = mem->probed_size;
1616 assert(devinfo->mem.sram.mem_class == mem->region.memory_class);
1617 assert(devinfo->mem.sram.mem_instance == mem->region.memory_instance);
1618 assert(devinfo->mem.sram.mappable.size == mem->probed_size);
1625 devinfo->mem.sram.mappable.free = MIN2(available, mem->probed_size);
1630 devinfo->mem.vram.mem_class = mem->region.memory_class;
1631 devinfo->mem.vram.mem_instance = mem->region.memory_instance;
1633 devinfo->mem.vram.mappable.size = mem->probed_cpu_visible_size;
1634 devinfo->mem.vram.unmappable.size =
1641 devinfo->mem.vram.mappable.size = mem->probed_size;
1642 devinfo->mem.vram.unmappable.size = 0;
1645 assert(devinfo->mem.vram.mem_class == mem->region.memory_class);
1646 assert(devinfo->mem.vram.mem_instance == mem->region.memory_instance);
1647 assert((devinfo->mem.vram.mappable.size +
1648 devinfo->mem.vram.unmappable.size) == mem->probed_size);
1652 devinfo->mem.vram.mappable.free = mem->unallocated_cpu_visible_size;
1653 devinfo->mem.vram.unmappable.free =
1662 devinfo->mem.vram.mappable.free = mem->unallocated_size;
1663 devinfo->mem.vram.unmappable.free = 0;
1673 devinfo->mem.use_class_instance = true;
1678 compute_system_memory(struct intel_device_info *devinfo, bool update)
1688 devinfo->mem.sram.mappable.size = total_phys;
1690 assert(devinfo->mem.sram.mappable.size == total_phys);
1692 devinfo->mem.sram.mappable.free = available;
1792 fixup_chv_device_info(struct intel_device_info *devinfo)
1794 assert(devinfo->platform == INTEL_PLATFORM_CHV);
1801 const uint32_t subslice_total = intel_device_info_subslice_total(devinfo);
1802 const uint32_t eu_total = intel_device_info_eu_total(devinfo);
1806 eu_total / subslice_total * devinfo->num_thread_per_eu;
1809 if (max_cs_threads > devinfo->max_cs_threads)
1810 devinfo->max_cs_threads = max_cs_threads;
1812 update_cs_workgroup_threads(devinfo);
1817 if (devinfo->pci_device_id != 0x22B1)
1827 char *needle = strstr(devinfo->name, "XXX");
1834 init_max_scratch_ids(struct intel_device_info *devinfo)
1842 * For Gfx9, devinfo->subslice_total is the TOTAL number of subslices and
1854 * For Gfx8 and older we user devinfo->subslice_total.
1857 if (devinfo->verx10 == 125)
1859 else if (devinfo->ver == 12)
1860 subslices = (devinfo->platform == INTEL_PLATFORM_DG1 || devinfo->gt == 2 ? 6 : 2);
1861 else if (devinfo->ver == 11)
1863 else if (devinfo->ver >= 9 && devinfo->ver < 11)
1864 subslices = 4 * devinfo->num_slices;
1866 subslices = devinfo->subslice_total;
1867 assert(subslices >= devinfo->subslice_total);
1870 if (devinfo->ver >= 12) {
1873 } else if (devinfo->ver >= 11) {
1885 } else if (devinfo->platform == INTEL_PLATFORM_HSW) {
1902 } else if (devinfo->platform == INTEL_PLATFORM_CHV) {
1909 scratch_ids_per_subslice = devinfo->max_cs_threads;
1914 if (devinfo->verx10 >= 125) {
1921 devinfo->max_scratch_ids[i] = max_thread_ids;
1924 [MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
1925 [MESA_SHADER_TESS_CTRL] = devinfo->max_tcs_threads,
1926 [MESA_SHADER_TESS_EVAL] = devinfo->max_tes_threads,
1927 [MESA_SHADER_GEOMETRY] = devinfo->max_gs_threads,
1928 [MESA_SHADER_FRAGMENT] = devinfo->max_wm_threads,
1931 STATIC_ASSERT(sizeof(devinfo->max_scratch_ids) == sizeof(max_scratch_ids));
1932 memcpy(devinfo->max_scratch_ids, max_scratch_ids,
1933 sizeof(devinfo->max_scratch_ids));
1938 intel_get_device_info_from_fd(int fd, struct intel_device_info *devinfo)
1955 (drmdev->deviceinfo.pci->device_id, devinfo)) {
1959 devinfo->pci_domain = drmdev->businfo.pci->domain;
1960 devinfo->pci_bus = drmdev->businfo.pci->bus;
1961 devinfo->pci_dev = drmdev->businfo.pci->dev;
1962 devinfo->pci_func = drmdev->businfo.pci->func;
1963 devinfo->pci_device_id = drmdev->deviceinfo.pci->device_id;
1964 devinfo->pci_revision_id = drmdev->deviceinfo.pci->revision_id;
1966 devinfo->no_hw = env_var_as_boolean("INTEL_NO_HW", false);
1968 if (devinfo->ver == 10) {
1974 if (devinfo->no_hw) {
1976 devinfo->gtt_size =
1977 devinfo->ver >= 8 ? (1ull << 48) : 2ull * 1024 * 1024 * 1024;
1978 compute_system_memory(devinfo, false);
1982 if (intel_get_and_process_hwconfig_table(fd, devinfo)) {
1984 devinfo->max_cs_threads =
1985 devinfo->max_eus_per_subslice * devinfo->num_thread_per_eu;
1987 update_cs_workgroup_threads(devinfo);
1993 devinfo->timestamp_frequency = timestamp_frequency;
1994 else if (devinfo->ver >= 10) {
1999 if (!getparam(fd, I915_PARAM_REVISION, &devinfo->revision))
2000 devinfo->revision = 0;
2002 if (!query_topology(devinfo, fd)) {
2003 if (devinfo->ver >= 10) {
2011 getparam_topology(devinfo, fd);
2017 if (!query_regions(devinfo, fd, false))
2018 compute_system_memory(devinfo, false);
2021 if (devinfo->has_local_mem && !devinfo->mem.use_class_instance) {
2026 if (devinfo->platform == INTEL_PLATFORM_CHV)
2027 fixup_chv_device_info(devinfo);
2040 devinfo->has_bit6_swizzle = devinfo->ver < 8 && has_bit6_swizzle(fd);
2042 intel_get_aperture_size(fd, &devinfo->aperture_bytes);
2043 get_context_param(fd, 0, I915_CONTEXT_PARAM_GTT_SIZE, &devinfo->gtt_size);
2044 devinfo->has_tiling_uapi = has_get_tiling(fd);
2047 assert(devinfo->subslice_total >= 1 || devinfo->ver <= 7);
2048 devinfo->subslice_total = MAX2(devinfo->subslice_total, 1);
2050 init_max_scratch_ids(devinfo);
2055 bool intel_device_info_update_memory_info(struct intel_device_info *devinfo, int fd)
2057 return query_regions(devinfo, fd, true) || compute_system_memory(devinfo, true);