genX_pipeline.c - OpenGrok cross reference for /third_party/mesa3d/src/intel/vulkan/genX

Lines Matching defs:devinfo
276    const struct intel_device_info *devinfo = &device->info;
281    intel_get_urb_config(devinfo, l3_config,
325    const struct intel_device_info *devinfo = &pipeline->base.device->info;
333       intel_get_mesh_urb_config(devinfo, pipeline->base.l3_config,
1021    const struct intel_device_info *devinfo = &pipeline->base.device->info;
1022    uint32_t *blend_state_start = devinfo->ver >= 8 ?
1517    const struct intel_device_info *devinfo = &pipeline->base.device->info;
1548       vs.MaximumNumberofThreads     = devinfo->max_vs_threads - 1;
1550       if (GFX_VER == 9 && devinfo->gt == 4 &&
1606    const struct intel_device_info *devinfo = &pipeline->base.device->info;
1630       assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances);
1633       hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1707       ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
1751    const struct intel_device_info *devinfo = &pipeline->base.device->info;
1778          gs.MaximumNumberofThreads = devinfo->max_gs_threads / 2 - 1;
1780          gs.MaximumNumberofThreads = devinfo->max_gs_threads - 1;
1908    const struct intel_device_info *devinfo = &pipeline->base.device->info;
1909    uint32_t *dws = devinfo->ver >= 8 ? pipeline->gfx8.wm : pipeline->gfx7.wm;
1918    UNUSED const struct intel_device_info *devinfo =
1929          ps.MaximumNumberofThreads = devinfo->max_wm_threads - 1;
2010          devinfo->max_threads_per_psd - (GFX_VER == 8 ? 2 : 1);
2012       ps.MaximumNumberofThreads        = devinfo->max_wm_threads - 1;
2186    const struct intel_device_info *devinfo = &pipeline->base.device->info;
2189       brw_cs_get_dispatch_info(devinfo, &task_prog_data->base, NULL);
2218       redistrib.TargetMeshBatchSize = devinfo->num_slices > 2 ? 3 : 5; /* 2^N */
2243    const struct intel_device_info *devinfo = &pipeline->base.device->info;
2246       brw_cs_get_dispatch_info(devinfo, &mesh_prog_data->base, NULL);
2295       distrib.TaskDistributionBatchSize = devinfo->num_slices > 2 ? 4 : 9; /* 2^N thread groups */
2296       distrib.MeshDistributionBatchSize = devinfo->num_slices > 2 ? 3 : 3; /* 2^N thread groups */
2392    const struct intel_device_info *devinfo = &device->info;
2396          devinfo->max_cs_threads * devinfo->subslice_total;
2408    const struct intel_device_info *devinfo = &device->info;
2414       brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
2428          devinfo->max_cs_threads * devinfo->subslice_total - 1;