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/third_party/libdrm/radeon/
H A Dradeon_surface.c96 struct radeon_surface *surf);
98 struct radeon_surface *surf);
167 static void surf_minify(struct radeon_surface *surf, in surf_minify() argument
173 surflevel->npix_x = mip_minify(surf->npix_x, level); in surf_minify()
174 surflevel->npix_y = mip_minify(surf->npix_y, level); in surf_minify()
175 surflevel->npix_z = mip_minify(surf->npix_z, level); in surf_minify()
176 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in surf_minify()
177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf in surf_minify()
266 r6_surface_init_linear(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, uint64_t offset, unsigned start_level) r6_surface_init_linear() argument
300 r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, uint64_t offset, unsigned start_level) r6_surface_init_linear_aligned() argument
328 r6_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, uint64_t offset, unsigned start_level) r6_surface_init_1d() argument
361 r6_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, uint64_t offset, unsigned start_level) r6_surface_init_2d() argument
404 r6_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) r6_surface_init() argument
474 r6_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) r6_surface_best() argument
570 eg_surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, unsigned slice_pt, unsigned mtilew, unsigned mtileh, unsigned mtileb, uint64_t offset) eg_surf_minify() argument
611 eg_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, uint64_t offset, unsigned start_level) eg_surface_init_1d() argument
652 eg_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_split, uint64_t offset, unsigned start_level) eg_surface_init_2d() argument
705 eg_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned mode) eg_surface_sanity() argument
788 eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) eg_surface_init_1d_miptrees() argument
810 eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) eg_surface_init_2d_miptrees() argument
833 eg_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) eg_surface_init() argument
908 eg_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) eg_surface_best() argument
1286 si_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) si_surface_sanity() argument
1421 si_surf_minify(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, uint32_t xalign, uint32_t yalign, uint32_t zalign, uint32_t slice_align, uint64_t offset) si_surf_minify() argument
1469 si_surf_minify_2d(struct radeon_surface *surf, struct radeon_surface_level *surflevel, unsigned bpe, unsigned level, unsigned slice_pt, uint32_t xalign, uint32_t yalign, uint32_t zalign, unsigned mtileb, uint64_t offset) si_surf_minify_2d() argument
1517 si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, uint64_t offset, unsigned start_level) si_surface_init_linear_aligned() argument
1550 si_surface_init_1d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, uint64_t offset, unsigned start_level) si_surface_init_1d() argument
1599 si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) si_surface_init_1d_miptrees() argument
1617 si_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned num_pipes, unsigned num_banks, unsigned tile_split, uint64_t offset, unsigned start_level) si_surface_init_2d() argument
1701 si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) si_surface_init_2d_miptrees() argument
1725 si_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) si_surface_init() argument
1785 si_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) si_surface_best() argument
2116 cik_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned mode, unsigned *tile_mode, unsigned *stencil_tile_mode) cik_surface_sanity() argument
2214 cik_surface_init_2d(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, struct radeon_surface_level *level, unsigned bpe, unsigned tile_mode, unsigned tile_split, unsigned num_pipes, unsigned num_banks, uint64_t offset, unsigned start_level) cik_surface_init_2d() argument
2303 cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned tile_mode, unsigned stencil_tile_mode) cik_surface_init_2d_miptrees() argument
2329 cik_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) cik_surface_init() argument
2389 cik_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) cik_surface_best() argument
2466 radeon_surface_sanity(struct radeon_surface_manager *surf_man, struct radeon_surface *surf, unsigned type, unsigned mode) radeon_surface_sanity() argument
2535 radeon_surface_init(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) radeon_surface_init() argument
2552 radeon_surface_best(struct radeon_surface_manager *surf_man, struct radeon_surface *surf) radeon_surface_best() argument
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/third_party/mesa3d/src/amd/common/
H A Dac_surface.c126 const struct radeon_surf *surf) in ac_surface_supports_dcc_image_stores()
151 return (!surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
152 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
153 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) || in ac_surface_supports_dcc_image_stores()
155 surf->u.gfx9.color.dcc.independent_64B_blocks && in ac_surface_supports_dcc_image_stores()
156 surf->u.gfx9.color.dcc.independent_128B_blocks && in ac_surface_supports_dcc_image_stores()
157 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B); in ac_surface_supports_dcc_image_stores()
169 ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf, in ac_modifier_fill_dcc_params() argument
186 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier); in ac_modifier_fill_dcc_params()
187 surf in ac_modifier_fill_dcc_params()
125 ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, const struct radeon_surf *surf) ac_surface_supports_dcc_image_stores() argument
630 gfx6_compute_level(ADDR_HANDLE addrlib, const struct ac_surf_config *config, struct radeon_surf *surf, bool is_stencil, unsigned level, bool compressed, ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn, ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut, ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn, ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut, ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn, ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut) gfx6_compute_level() argument
843 gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct radeon_info *info) gfx6_set_micro_tile_mode() argument
853 cik_get_macro_tile_index(struct radeon_surf *surf) cik_get_macro_tile_index() argument
867 get_display_flag(const struct ac_surf_config *config, const struct radeon_surf *surf) get_display_flag() argument
904 gfx6_surface_settings(ADDR_HANDLE addrlib, const struct radeon_info *info, const struct ac_surf_config *config, ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf) gfx6_surface_settings() argument
953 ac_compute_cmask(const struct radeon_info *info, const struct ac_surf_config *config, struct radeon_surf *surf) ac_compute_cmask() argument
1020 gfx6_compute_surface(ADDR_HANDLE addrlib, const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) gfx6_compute_surface() argument
1415 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib, const struct radeon_info *info, struct radeon_surf *surf, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in, bool is_fmask, AddrSwizzleMode *swizzle_mode) gfx9_get_preferred_swizzle_mode() argument
1522 is_dcc_supported_by_L2(const struct radeon_info *info, const struct radeon_surf *surf) is_dcc_supported_by_L2() argument
1590 is_dcc_supported_by_DCN(const struct radeon_info *info, const struct ac_surf_config *config, const struct radeon_surf *surf, bool rb_aligned, bool pipe_aligned) is_dcc_supported_by_DCN() argument
1708 gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_info *info, const struct ac_surf_config *config, struct radeon_surf *surf, bool compressed, ADDR2_COMPUTE_SURFACE_INFO_INPUT *in) gfx9_compute_miptree() argument
2134 gfx9_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) gfx9_compute_surface() argument
2487 ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, const struct ac_surf_config *config, enum radeon_surf_mode mode, struct radeon_surf *surf) ac_compute_surface() argument
2552 ac_surface_zero_dcc_fields(struct radeon_surf *surf) ac_surface_zero_dcc_fields() argument
2619 ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, uint64_t tiling_flags, enum radeon_surf_mode *mode) ac_surface_set_bo_metadata() argument
2659 ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, uint64_t *tiling_flags) ac_surface_get_bo_metadata() argument
2712 ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, unsigned num_storage_samples, unsigned num_mipmap_levels, unsigned size_metadata, const uint32_t metadata[64]) ac_surface_set_umd_metadata() argument
2804 ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, unsigned num_mipmap_levels, uint32_t desc[8], unsigned *size_metadata, uint32_t metadata[64]) ac_surface_get_umd_metadata() argument
2863 ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf) ac_surface_get_gfx9_pitch_align() argument
2889 ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, unsigned num_mipmap_levels, uint64_t offset, unsigned pitch) ac_surface_override_offset_stride() argument
2953 ac_surface_get_nplanes(const struct radeon_surf *surf) ac_surface_get_nplanes() argument
2965 ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned layer) ac_surface_get_plane_offset() argument
2990 ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, const struct radeon_surf *surf, unsigned plane, unsigned level) ac_surface_get_plane_stride() argument
3011 ac_surface_get_plane_size(const struct radeon_surf *surf, unsigned plane) ac_surface_get_plane_size() argument
3027 ac_surface_print_info(FILE *out, const struct radeon_info *info, const struct radeon_surf *surf) ac_surface_print_info() argument
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H A Dac_surface_modifier_test.c69 get_addr_from_coord_base(ADDR_HANDLE addrlib, const struct radeon_surf *surf, in get_addr_from_coord_base() argument
78 din.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned; in get_addr_from_coord_base()
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned; in get_addr_from_coord_base()
88 din.dataSurfaceSize = surf->surf_size; in get_addr_from_coord_base()
95 dcc_input.swizzleMode = surf->u.gfx9.swizzle_mode; in get_addr_from_coord_base()
117 const struct radeon_surf *surf) in generate_hash()
125 _mesa_sha1_update(&ctx, &surf->total_size, sizeof(surf->total_size)); in generate_hash()
126 _mesa_sha1_update(&ctx, &surf in generate_hash()
115 generate_hash(struct ac_addrlib *ac_addrlib, struct test_entry *entry, const struct radeon_surf *surf) generate_hash() argument
248 struct radeon_surf surf = (struct radeon_surf) { test_modifier() local
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/third_party/mesa3d/src/intel/isl/tests/
H A Disl_surf_get_image_offset_test.c55 t_assert_image_alignment_el(const struct isl_surf *surf, in t_assert_image_alignment_el() argument
60 align_el = isl_surf_get_image_alignment_el(surf); in t_assert_image_alignment_el()
68 t_assert_image_alignment_sa(const struct isl_surf *surf, in t_assert_image_alignment_sa() argument
73 align_sa = isl_surf_get_image_alignment_sa(surf); in t_assert_image_alignment_sa()
81 t_assert_offset_el(const struct isl_surf *surf, in t_assert_offset_el() argument
89 isl_surf_get_image_offset_el(surf, level, logical_array_layer, in t_assert_offset_el()
97 t_assert_phys_level0_sa(const struct isl_surf *surf, uint32_t width, in t_assert_phys_level0_sa() argument
100 t_assert_extent4d(&surf->phys_level0_sa, width, height, depth, array_len); in t_assert_phys_level0_sa()
104 t_assert_gfx4_3d_layer(const struct isl_surf *surf, in t_assert_gfx4_3d_layer() argument
114 t_assert_offset_el(surf, leve in t_assert_gfx4_3d_layer()
133 struct isl_surf surf; test_bdw_2d_r8g8b8a8_unorm_512x512_array01_samples01_noaux_tiley0() local
181 struct isl_surf surf; test_bdw_2d_r8g8b8a8_unorm_1024x1024_array06_samples01_noaux_tiley0() local
242 struct isl_surf surf; test_bdw_3d_r8g8b8a8_unorm_256x256x256_levels09_tiley0() local
[all...]
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_surface.c92 struct etna_surface *surf = CALLOC_STRUCT(etna_surface); in etna_create_surface() local
94 if (!surf) in etna_create_surface()
100 surf->base.context = pctx; in etna_create_surface()
102 pipe_reference_init(&surf->base.reference, 1); in etna_create_surface()
103 pipe_resource_reference(&surf->base.texture, &rsc->base); in etna_create_surface()
104 pipe_resource_reference(&surf->prsc, prsc); in etna_create_surface()
121 surf->base.format = templat->format; in etna_create_surface()
122 surf->base.width = rsc->levels[level].width; in etna_create_surface()
123 surf->base.height = rsc->levels[level].height; in etna_create_surface()
124 surf in etna_create_surface()
[all...]
H A Detnaviv_rs.c278 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf, in etna_rs_gen_clear_surface() argument
282 struct etna_resource *dst = etna_resource(surf->base.texture); in etna_rs_gen_clear_surface()
285 switch (util_format_get_blocksizebits(surf->base.format)) { in etna_rs_gen_clear_surface()
302 bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 && in etna_rs_gen_clear_surface()
303 (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0; in etna_rs_gen_clear_surface()
305 etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) { in etna_rs_gen_clear_surface()
309 .dest_offset = surf->surf in etna_rs_gen_clear_surface()
327 struct etna_surface *surf = etna_surface(dst); etna_blit_clear_color_rs() local
360 struct etna_surface *surf = etna_surface(dst); etna_blit_clear_zs_rs() local
434 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]); etna_clear_rs() local
439 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf); etna_clear_rs() local
[all...]
H A Detnaviv_blt.c217 struct etna_surface *surf = etna_surface(dst); in etna_blit_clear_color_blt() local
218 uint64_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color); in etna_blit_clear_color_blt()
220 struct etna_resource *res = etna_resource(surf->base.texture); in etna_blit_clear_color_blt()
223 clr.dest.addr.offset = surf->surf.offset; in etna_blit_clear_color_blt()
225 clr.dest.bpp = util_format_get_blocksize(surf->base.format); in etna_blit_clear_color_blt()
226 clr.dest.stride = surf->surf.stride; in etna_blit_clear_color_blt()
229 if (surf->surf in etna_blit_clear_color_blt()
269 struct etna_surface *surf = etna_surface(dst); etna_blit_clear_zs_blt() local
[all...]
/third_party/mesa3d/src/egl/main/
H A Deglsurface.c54 _eglParseSurfaceAttribList(_EGLSurface *surf, const EGLint *attrib_list) in _eglParseSurfaceAttribList() argument
56 _EGLDisplay *disp = surf->Resource.Display; in _eglParseSurfaceAttribList()
57 EGLint type = surf->Type; in _eglParseSurfaceAttribList()
89 surf->GLColorspace = val; in _eglParseSurfaceAttribList()
96 surf->HdrMetadata.display_primary_r.x = val; in _eglParseSurfaceAttribList()
103 surf->HdrMetadata.display_primary_r.y = val; in _eglParseSurfaceAttribList()
110 surf->HdrMetadata.display_primary_g.x = val; in _eglParseSurfaceAttribList()
117 surf->HdrMetadata.display_primary_g.y = val; in _eglParseSurfaceAttribList()
124 surf->HdrMetadata.display_primary_b.x = val; in _eglParseSurfaceAttribList()
131 surf in _eglParseSurfaceAttribList()
359 _eglInitSurface(_EGLSurface *surf, _EGLDisplay *disp, EGLint type, _EGLConfig *conf, const EGLint *attrib_list, void *native_surface) _eglInitSurface() argument
785 _eglReleaseTexImage(_EGLDisplay *disp, _EGLSurface *surf, EGLint buffer) _eglReleaseTexImage() argument
820 _eglSurfaceHasMutableRenderBuffer(_EGLSurface *surf) _eglSurfaceHasMutableRenderBuffer() argument
828 _eglSurfaceInSharedBufferMode(_EGLSurface *surf) _eglSurfaceInSharedBufferMode() argument
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H A Deglsurface.h181 _eglInitSurface(_EGLSurface *surf, _EGLDisplay *disp, EGLint type,
187 _eglQuerySurface(_EGLDisplay *disp, _EGLSurface *surf, EGLint attribute, EGLint *value);
191 _eglSurfaceAttrib(_EGLDisplay *disp, _EGLSurface *surf, EGLint attribute, EGLint value);
195 _eglBindTexImage(_EGLDisplay *disp, _EGLSurface *surf, EGLint buffer);
198 _eglReleaseTexImage(_EGLDisplay *disp, _EGLSurface *surf, EGLint buffer);
202 _eglSurfaceHasMutableRenderBuffer(_EGLSurface *surf);
205 _eglSurfaceInSharedBufferMode(_EGLSurface *surf);
211 _eglGetSurface(_EGLSurface *surf) in _eglGetSurface() argument
213 if (surf) in _eglGetSurface()
214 _eglGetResource(&surf in _eglGetSurface()
223 _eglPutSurface(_EGLSurface *surf) _eglPutSurface() argument
234 _eglLinkSurface(_EGLSurface *surf) _eglLinkSurface() argument
246 _eglUnlinkSurface(_EGLSurface *surf) _eglUnlinkSurface() argument
259 _EGLSurface *surf = (_EGLSurface *) surface; _eglLookupSurface() local
270 _eglGetSurfaceHandle(_EGLSurface *surf) _eglGetSurfaceHandle() argument
[all...]
/third_party/mesa3d/src/intel/isl/
H A Disl_genX_helpers.h82 isl_get_image_alignment(const struct isl_surf *surf) in isl_get_image_alignment() argument
85 if (surf->tiling == ISL_TILING_64) { in isl_get_image_alignment()
91 } else if (isl_format_get_layout(surf->format)->bpb % 3 == 0) { in isl_get_image_alignment()
95 return isl_surf_get_image_alignment_el(surf); in isl_get_image_alignment()
100 const uint32_t bs = isl_format_get_layout(surf->format)->bpb / 8; in isl_get_image_alignment()
101 return isl_extent3d(surf->image_alignment_el.w * bs, in isl_get_image_alignment()
102 surf->image_alignment_el.h, in isl_get_image_alignment()
103 surf->image_alignment_el.d); in isl_get_image_alignment()
106 if (isl_tiling_is_std_y(surf->tiling) || in isl_get_image_alignment()
107 surf in isl_get_image_alignment()
135 isl_get_qpitch(const struct isl_surf *surf) isl_get_qpitch() argument
[all...]
H A Disl.c1806 struct isl_surf *surf, in isl_surf_init_s()
1981 *surf = (struct isl_surf) { in isl_surf_init_s()
2008 isl_surf_get_tile_info(const struct isl_surf *surf, in isl_surf_get_tile_info() argument
2011 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); in isl_surf_get_tile_info()
2012 isl_tiling_get_info(surf->tiling, surf->dim, surf->msaa_layout, fmtl->bpb, in isl_surf_get_tile_info()
2013 surf->samples, tile_info); in isl_surf_get_tile_info()
2018 const struct isl_surf *surf, in isl_surf_get_hiz_surf()
2025 if (!isl_surf_usage_is_depth(surf in isl_surf_get_hiz_surf()
1805 isl_surf_init_s(const struct isl_device *dev, struct isl_surf *surf, const struct isl_surf_init_info *restrict info) isl_surf_init_s() argument
2017 isl_surf_get_hiz_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *hiz_surf) isl_surf_get_hiz_surf() argument
2092 isl_surf_get_mcs_surf(const struct isl_device *dev, const struct isl_surf *surf, struct isl_surf *mcs_surf) isl_surf_get_mcs_surf() argument
2135 isl_surf_supports_ccs(const struct isl_device *dev, const struct isl_surf *surf, const struct isl_surf *hiz_or_mcs_surf) isl_surf_supports_ccs() argument
2293 isl_surf_get_ccs_surf(const struct isl_device *dev, const struct isl_surf *surf, const struct isl_surf *hiz_or_mcs_surf, struct isl_surf *ccs_surf, uint32_t row_pitch_B) isl_surf_get_ccs_surf() argument
2510 get_image_offset_sa_gfx4_2d(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t *x_offset_sa, uint32_t *y_offset_sa) get_image_offset_sa_gfx4_2d() argument
2552 get_image_offset_sa_gfx4_3d(const struct isl_surf *surf, uint32_t level, uint32_t logical_z_offset_px, uint32_t *x_offset_sa, uint32_t *y_offset_sa) get_image_offset_sa_gfx4_3d() argument
2605 get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t *x_offset_sa, uint32_t *y_offset_sa) get_image_offset_sa_gfx6_stencil_hiz() argument
2668 get_image_offset_sa_gfx9_1d(const struct isl_surf *surf, uint32_t level, uint32_t layer, uint32_t *x_offset_sa, uint32_t *y_offset_sa) get_image_offset_sa_gfx9_1d() argument
2705 isl_surf_get_image_offset_sa(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_sa, uint32_t *y_offset_sa, uint32_t *z_offset_sa, uint32_t *array_offset) isl_surf_get_image_offset_sa() argument
2754 isl_surf_get_image_offset_el(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint32_t *x_offset_el, uint32_t *y_offset_el, uint32_t *z_offset_el, uint32_t *array_offset) isl_surf_get_image_offset_el() argument
2785 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint64_t *offset_B, uint32_t *x_offset_sa, uint32_t *y_offset_sa) isl_surf_get_image_offset_B_tile_sa() argument
2817 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint64_t *offset_B, uint32_t *x_offset_el, uint32_t *y_offset_el) isl_surf_get_image_offset_B_tile_el() argument
2856 isl_surf_get_image_range_B_tile(const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, uint64_t *start_tile_B, uint64_t *end_tile_B) isl_surf_get_image_range_B_tile() argument
2927 isl_surf_get_image_surf(const struct isl_device *dev, const struct isl_surf *surf, uint32_t level, uint32_t logical_array_layer, uint32_t logical_z_offset_px, struct isl_surf *image_surf, uint64_t *offset_B, uint32_t *x_offset_sa, uint32_t *y_offset_sa) isl_surf_get_image_surf() argument
2968 isl_surf_get_uncompressed_surf(const struct isl_device *dev, const struct isl_surf *surf, const struct isl_view *view, struct isl_surf *ucompr_surf, struct isl_view *ucompr_view, uint64_t *offset_B, uint32_t *x_offset_el, uint32_t *y_offset_el) isl_surf_get_uncompressed_surf() argument
3174 isl_surf_get_depth_format(const struct isl_device *dev, const struct isl_surf *surf) isl_surf_get_depth_format() argument
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H A Disl_storage_image.c226 const struct isl_surf *surf, in isl_surf_fill_image_param()
231 if (surf->dim != ISL_SURF_DIM_3D) { in isl_surf_fill_image_param()
233 surf->logical_level0_px.array_len); in isl_surf_fill_image_param()
235 param->size[0] = isl_minify(surf->logical_level0_px.w, view->base_level); in isl_surf_fill_image_param()
236 param->size[1] = surf->dim == ISL_SURF_DIM_1D ? in isl_surf_fill_image_param()
238 isl_minify(surf->logical_level0_px.h, view->base_level); in isl_surf_fill_image_param()
239 param->size[2] = surf->dim == ISL_SURF_DIM_2D ? in isl_surf_fill_image_param()
241 isl_minify(surf->logical_level0_px.d, view->base_level); in isl_surf_fill_image_param()
244 isl_surf_get_image_offset_el(surf, view->base_level, in isl_surf_fill_image_param()
245 surf in isl_surf_fill_image_param()
224 isl_surf_fill_image_param(const struct isl_device *dev, struct brw_image_param *param, const struct isl_surf *surf, const struct isl_view *view) isl_surf_fill_image_param() argument
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/third_party/mesa3d/src/mesa/main/
H A Dvdpau.c87 struct vdp_surface *surf = (struct vdp_surface *)entry->key; in unregister_surface() local
90 if (surf->state == GL_SURFACE_MAPPED_NV) { in unregister_surface()
91 GLintptr surfaces[] = { (GLintptr)surf }; in unregister_surface()
96 FREE(surf); in unregister_surface()
121 struct vdp_surface *surf; in register_surface() local
139 surf = CALLOC_STRUCT( vdp_surface ); in register_surface()
140 if (surf == NULL) { in register_surface()
145 surf->vdpSurface = vdpSurface; in register_surface()
146 surf->target = target; in register_surface()
147 surf in register_surface()
228 struct vdp_surface *surf = (struct vdp_surface *)surface; _mesa_VDPAUIsSurfaceNV() local
246 struct vdp_surface *surf = (struct vdp_surface *)surface; _mesa_VDPAUUnregisterSurfaceNV() local
281 struct vdp_surface *surf = (struct vdp_surface *)surface; _mesa_VDPAUGetSurfaceivNV() local
313 struct vdp_surface *surf = (struct vdp_surface *)surface; _mesa_VDPAUSurfaceAccessNV() local
353 struct vdp_surface *surf = (struct vdp_surface *)surfaces[i]; _mesa_VDPAUMapSurfacesNV() local
367 struct vdp_surface *surf = (struct vdp_surface *)surfaces[i]; _mesa_VDPAUMapSurfacesNV() local
407 struct vdp_surface *surf = (struct vdp_surface *)surfaces[i]; _mesa_VDPAUUnmapSurfacesNV() local
421 struct vdp_surface *surf = (struct vdp_surface *)surfaces[i]; _mesa_VDPAUUnmapSurfacesNV() local
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/third_party/mesa3d/src/intel/blorp/
H A Dblorp.c98 const struct blorp_surf *surf, in brw_blorp_surface_info_init()
104 assert(level < surf->surf->levels); in brw_blorp_surface_info_init()
105 assert(layer < MAX2(surf->surf->logical_level0_px.depth >> level, in brw_blorp_surface_info_init()
106 surf->surf->logical_level0_px.array_len)); in brw_blorp_surface_info_init()
111 format = surf->surf->format; in brw_blorp_surface_info_init()
113 info->surf in brw_blorp_surface_info_init()
96 brw_blorp_surface_info_init(struct blorp_batch *batch, struct brw_blorp_surface_info *info, const struct blorp_surf *surf, unsigned int level, float layer, enum isl_format format, bool is_dest) brw_blorp_surface_info_init() argument
407 blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf, uint32_t level, uint32_t start_layer, uint32_t num_layers, enum isl_aux_op op) blorp_hiz_op() argument
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H A Dblorp_clear.c304 const struct isl_surf *surf, in get_fast_clear_rect()
313 if (surf->samples == 1) { in get_fast_clear_rect()
315 assert(surf->tiling == ISL_TILING_4); in get_fast_clear_rect()
326 const uint32_t bs = isl_format_get_layout(surf->format)->bpb / 8; in get_fast_clear_rect()
449 const struct blorp_surf *surf, in blorp_fast_clear()
467 get_fast_clear_rect(batch->blorp->isl_dev, surf->surf, surf->aux_surf, in blorp_fast_clear()
473 brw_blorp_surface_info_init(batch, &params.dst, surf, level, in blorp_fast_clear()
475 params.num_samples = params.dst.surf in blorp_fast_clear()
303 get_fast_clear_rect(const struct isl_device *dev, const struct isl_surf *surf, const struct isl_surf *aux_surf, unsigned *x0, unsigned *y0, unsigned *x1, unsigned *y1) get_fast_clear_rect() argument
448 blorp_fast_clear(struct blorp_batch *batch, const struct blorp_surf *surf, enum isl_format format, struct isl_swizzle swizzle, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) blorp_fast_clear() argument
511 blorp_clear(struct blorp_batch *batch, const struct blorp_surf *surf, enum isl_format format, struct isl_swizzle swizzle, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, union isl_color_value clear_color, uint8_t color_write_disable) blorp_clear() argument
706 blorp_clear_stencil_as_rgba(struct blorp_batch *batch, const struct blorp_surf *surf, uint32_t level, uint32_t start_layer, uint32_t num_layers, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1, uint8_t stencil_mask, uint8_t stencil_value) blorp_clear_stencil_as_rgba() argument
903 blorp_can_hiz_clear_depth(const struct intel_device_info *devinfo, const struct isl_surf *surf, enum isl_aux_usage aux_usage, uint32_t level, uint32_t layer, uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1) blorp_can_hiz_clear_depth() argument
1176 blorp_ccs_resolve(struct blorp_batch *batch, struct blorp_surf *surf, uint32_t level, uint32_t start_layer, uint32_t num_layers, enum isl_format format, enum isl_aux_op resolve_op) blorp_ccs_resolve() argument
1361 blorp_mcs_partial_resolve(struct blorp_batch *batch, struct blorp_surf *surf, enum isl_format format, uint32_t start_layer, uint32_t num_layers) blorp_mcs_partial_resolve() argument
1402 blorp_ccs_ambiguate(struct blorp_batch *batch, struct blorp_surf *surf, uint32_t level, uint32_t layer) blorp_ccs_ambiguate() argument
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/third_party/skia/tests/
H A DWrappedSurfaceCopyOnWriteTest.cpp38 auto surfaceProxyID = [&](const sk_sp<SkSurface>& surf) { in DEF_GPUTEST_FOR_ALL_CONTEXTS()
39 GrRenderTargetProxy* rtp = SkCanvasPriv::TopDeviceTargetProxy(surf->getCanvas()); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
43 sk_sp<SkSurface> surf = makeDirectBackendSurface(); in DEF_GPUTEST_FOR_ALL_CONTEXTS() local
44 surf->getCanvas()->clear(SkColor4f{1, 0, 0, 1}); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
45 sk_sp<SkImage> img = surf->makeImageSnapshot(); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
47 REPORTER_ASSERT(reporter, surfaceProxyID(surf) == imageProxyID(img)); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
51 REPORTER_ASSERT(reporter, surfaceProxyID(surf) == imageProxyID(img)); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
53 surf->getCanvas()->clear({0, 0, 1, 1}); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
54 REPORTER_ASSERT(reporter, surfaceProxyID(surf) != imageProxyID(img)); in DEF_GPUTEST_FOR_ALL_CONTEXTS()
57 img = surf in DEF_GPUTEST_FOR_ALL_CONTEXTS()
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H A DSpecialSurfaceTest.cpp20 static const SkIRect& Subset(const SkSpecialSurface* surf) { in Subset() argument
21 return surf->subset(); in Subset()
32 static void test_surface(const sk_sp<SkSpecialSurface>& surf, in test_surface() argument
36 const SkIRect surfSubset = TestingSpecialSurfaceAccess::Subset(surf.get()); in test_surface()
42 SkCanvas* canvas = surf->getCanvas(); in test_surface()
47 sk_sp<SkSpecialImage> img(surf->makeImageSnapshot()); in test_surface()
54 REPORTER_ASSERT(reporter, !surf->getCanvas()); in test_surface()
60 sk_sp<SkSpecialSurface> surf(SkSpecialSurface::MakeRaster(info, SkSurfaceProps())); in DEF_TEST()
62 test_surface(surf, reporter, 0); in DEF_TEST()
72 sk_sp<SkSpecialSurface> surf(SkSpecialSurfac in DEF_TEST()
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H A DGrTextureMipMapInvalidationTest.cpp25 auto isMipped = [reporter](SkSurface* surf) { in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
26 sk_sp<SkImage> image = surf->makeImageSnapshot(); in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
28 surf->recordingContext()); in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
34 auto mipsAreDirty = [](SkSurface* surf) { in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
35 sk_sp<SkImage> image = surf->makeImageSnapshot(); in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
37 surf->recordingContext()); in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
79 auto surf = SkSurface::MakeRenderTarget( in DEF_GPUTEST_FOR_RENDERING_CONTEXTS() local
83 if (!surf) { in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
86 surf->getCanvas()->drawColor(SK_ColorDKGRAY); in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
87 auto img = surf in DEF_GPUTEST_FOR_RENDERING_CONTEXTS()
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/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_blt.c51 const struct isl_format_layout *fmtl = isl_format_get_layout(dst->surf.format); in blt_set_alpha_to_one()
53 uint32_t pitch = dst->surf.row_pitch_B; in blt_set_alpha_to_one()
55 if (dst->surf.tiling != ISL_TILING_LINEAR) in blt_set_alpha_to_one()
72 isl_tiling_get_intratile_offset_el(dst->surf.tiling, dst->surf.dim, in blt_set_alpha_to_one()
73 dst->surf.msaa_layout, in blt_set_alpha_to_one()
74 cpp * 8, dst->surf.samples, in blt_set_alpha_to_one()
75 dst->surf.row_pitch_B, in blt_set_alpha_to_one()
76 dst->surf.array_pitch_el_rows, in blt_set_alpha_to_one()
84 xyblt.TilingEnable = dst->surf in blt_set_alpha_to_one()
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/third_party/skia/gm/
H A Dsurface.cpp150 auto surf(ToolUtils::makeSurface(canvas, info, nullptr));
151 drawInto(surf->getCanvas());
153 sk_sp<SkImage> image(surf->makeImageSnapshot());
156 auto surf2(surf->makeSurface(info));
160 SkASSERT(equal(surf->props(), surf2->props()));
243 sk_sp<SkSurface> surf = make(info); in DEF_SURFACE_TESTS() local
245 surf->getCanvas()->clear(SK_ColorRED); in DEF_SURFACE_TESTS()
248 sk_sp<SkImage> image = surf->makeImageSnapshot(); in DEF_SURFACE_TESTS()
252 surf->getCanvas()->clipRect(SkRect::MakeWH(128, 256)); in DEF_SURFACE_TESTS()
253 surf in DEF_SURFACE_TESTS()
262 sk_sp<SkSurface> surf = make(info); DEF_SURFACE_TESTS() local
281 sk_sp<SkSurface> surf = make(info); DEF_SURFACE_TESTS() local
292 sk_sp<SkSurface> surf = make(info); DEF_SURFACE_TESTS() local
303 sk_sp<SkSurface> surf = make(info); DEF_SURFACE_TESTS() local
324 auto surf = make(info); DEF_SURFACE_TESTS() local
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/third_party/mesa3d/src/gallium/drivers/vc4/kernel/
H A Dvc4_render_cl.c94 struct drm_vc4_submit_rcl_surface *surf, in vc4_full_res_offset()
97 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * in vc4_full_res_offset()
379 struct drm_vc4_submit_rcl_surface *surf) in vc4_full_res_bounds_check()
385 if (surf->offset > obj->base.size) { in vc4_full_res_bounds_check()
387 surf->offset, obj->base.size); in vc4_full_res_bounds_check()
391 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < in vc4_full_res_bounds_check()
397 surf->offset); in vc4_full_res_bounds_check()
406 struct drm_vc4_submit_rcl_surface *surf) in vc4_rcl_msaa_surface_setup()
408 if (surf->flags != 0 || surf in vc4_rcl_msaa_surface_setup()
92 vc4_full_res_offset(struct vc4_exec_info *exec, struct drm_gem_cma_object *bo, struct drm_vc4_submit_rcl_surface *surf, uint8_t x, uint8_t y) vc4_full_res_offset() argument
377 vc4_full_res_bounds_check(struct vc4_exec_info *exec, struct drm_gem_cma_object *obj, struct drm_vc4_submit_rcl_surface *surf) vc4_full_res_bounds_check() argument
404 vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, struct drm_gem_cma_object **obj, struct drm_vc4_submit_rcl_surface *surf) vc4_rcl_msaa_surface_setup() argument
428 vc4_rcl_surface_setup(struct vc4_exec_info *exec, struct drm_gem_cma_object **obj, struct drm_vc4_submit_rcl_surface *surf) vc4_rcl_surface_setup() argument
523 vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, struct vc4_rcl_setup *setup, struct drm_gem_cma_object **obj, struct drm_vc4_submit_rcl_surface *surf) vc4_rcl_render_config_surface_setup() argument
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/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_resolve.c62 struct iris_surface *surf = (void *) cso_fb->cbufs[i]; in disable_rb_aux_buffer() local
63 if (!surf) in disable_rb_aux_buffer()
66 struct iris_resource *rb_res = (void *) surf->base.texture; in disable_rb_aux_buffer()
69 surf->base.u.tex.level >= min_level && in disable_rb_aux_buffer()
70 surf->base.u.tex.level < min_level + num_levels) { in disable_rb_aux_buffer()
220 struct iris_surface *surf = (void *) cso_fb->cbufs[i]; in iris_predraw_resolve_framebuffer() local
223 iris_resource_prepare_texture(ice, res, surf->view.format, in iris_predraw_resolve_framebuffer()
224 surf->view.base_level, 1, in iris_predraw_resolve_framebuffer()
225 surf->view.base_array_layer, in iris_predraw_resolve_framebuffer()
226 surf in iris_predraw_resolve_framebuffer()
233 struct iris_surface *surf = (void *) cso_fb->cbufs[i]; iris_predraw_resolve_framebuffer() local
313 struct iris_surface *surf = (void *) cso_fb->cbufs[i]; iris_postdraw_update_resolve_tracking() local
438 struct blorp_surf surf; iris_resolve_color() local
501 struct blorp_surf surf; iris_mcs_partial_resolve() local
611 struct blorp_surf surf; iris_hiz_exec() local
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/third_party/mesa3d/src/gallium/drivers/v3d/
H A Dv3dx_rcl.c58 struct v3d_surface *surf = v3d_surface(psurf); in load_general() local
59 bool separate_stencil = surf->separate_stencil && buffer == STENCIL; in load_general()
61 psurf = surf->separate_stencil; in load_general()
62 surf = v3d_surface(psurf); in load_general()
75 load.memory_format = surf->tiling; in load_general()
79 load.input_image_format = surf->format; in load_general()
80 load.r_b_swap = surf->swap_rb; in load_general()
82 if (surf->tiling == V3D_TILING_UIF_NO_XOR || in load_general()
83 surf->tiling == V3D_TILING_UIF_XOR) { in load_general()
85 surf in load_general()
120 struct v3d_surface *surf = v3d_surface(psurf); store_general() local
494 struct v3d_surface *surf = v3d_surface(job->cbufs[cbuf]); v3d_setup_render_target() local
507 v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf, struct v3d_resource *rsc, bool is_separate_stencil) v3d_emit_z_stencil_config() argument
778 struct v3d_surface *surf = v3d_surface(psurf); emit_rcl() local
870 struct v3d_surface *surf = v3d_surface(psurf); emit_rcl() local
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/third_party/mesa3d/src/gallium/frontends/vdpau/
H A Dpresentation.c209 vlVdpOutputSurface *surf; in vlVdpPresentationQueueDisplay() local
224 surf = vlGetDataHTAB(surface); in vlVdpPresentationQueueDisplay()
225 if (!surf) in vlVdpPresentationQueueDisplay()
234 if (vscreen->set_back_texture_from_output && surf->send_to_X) in vlVdpPresentationQueueDisplay()
235 vscreen->set_back_texture_from_output(vscreen, surf->surface->texture, clip_width, clip_height); in vlVdpPresentationQueueDisplay()
242 if (!vscreen->set_back_texture_from_output || !surf->send_to_X) { in vlVdpPresentationQueueDisplay()
260 vl_compositor_set_rgba_layer(cstate, compositor, 0, surf->sampler_view, &src_rect, NULL, NULL); in vlVdpPresentationQueueDisplay()
269 pipe->screen->fence_reference(pipe->screen, &surf->fence, NULL); in vlVdpPresentationQueueDisplay()
270 pipe->flush(pipe, &surf->fence, 0); in vlVdpPresentationQueueDisplay()
274 pq->last_surf = surf; in vlVdpPresentationQueueDisplay()
310 vlVdpOutputSurface *surf; vlVdpPresentationQueueBlockUntilSurfaceIdle() local
345 vlVdpOutputSurface *surf; vlVdpPresentationQueueQuerySurfaceStatus() local
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/third_party/mesa3d/src/gallium/frontends/va/
H A Dimage.c200 vlVaSurface *surf; in vlVaDeriveImage() local
243 surf = handle_table_get(drv->htab, surface); in vlVaDeriveImage()
245 if (!surf || !surf->buffer) in vlVaDeriveImage()
248 if (surf->buffer->interlaced) { in vlVaDeriveImage()
267 surfaces = surf->buffer->get_surfaces(surf->buffer); in vlVaDeriveImage()
275 img->format.fourcc = PipeFormatToVaFourcc(surf->buffer->buffer_format); in vlVaDeriveImage()
278 img->width = surf->templat.width; in vlVaDeriveImage()
279 img->height = surf in vlVaDeriveImage()
471 vlVaSurface *surf; vlVaGetImage() local
615 vlVaSurface *surf; vlVaPutImage() local
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