Lines Matching refs:surf
1806 struct isl_surf *surf,
1981 *surf = (struct isl_surf) {
2008 isl_surf_get_tile_info(const struct isl_surf *surf,
2011 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2012 isl_tiling_get_info(surf->tiling, surf->dim, surf->msaa_layout, fmtl->bpb,
2013 surf->samples, tile_info);
2018 const struct isl_surf *surf,
2025 if (!isl_surf_usage_is_depth(surf->usage))
2037 if (isl_surf_usage_is_stencil(surf->usage))
2041 assert(surf->msaa_layout == ISL_MSAA_LAYOUT_NONE ||
2042 surf->msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
2073 const unsigned samples = ISL_GFX_VER(dev) >= 9 ? 1 : surf->samples;
2079 .dim = surf->dim,
2081 .width = surf->logical_level0_px.width,
2082 .height = surf->logical_level0_px.height,
2083 .depth = surf->logical_level0_px.depth,
2084 .levels = surf->levels,
2085 .array_len = surf->logical_level0_px.array_len,
2093 const struct isl_surf *surf,
2097 if (surf->msaa_layout != ISL_MSAA_LAYOUT_ARRAY)
2105 assert(surf->samples > 1);
2106 assert(surf->dim == ISL_SURF_DIM_2D);
2107 assert(surf->levels == 1);
2108 assert(surf->logical_level0_px.depth == 1);
2109 assert(isl_format_supports_multisampling(dev->info, surf->format));
2112 switch (surf->samples) {
2124 .width = surf->logical_level0_px.width,
2125 .height = surf->logical_level0_px.height,
2128 .array_len = surf->logical_level0_px.array_len,
2136 const struct isl_surf *surf,
2139 if (surf->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT)
2142 if (!isl_format_supports_ccs_d(dev->info, surf->format) &&
2143 !isl_format_supports_ccs_e(dev->info, surf->format))
2165 if (surf->tiling == ISL_TILING_LINEAR)
2171 if (isl_surf_usage_is_cpb(surf->usage))
2175 if (isl_surf_usage_is_stencil(surf->usage)) {
2180 if (surf->samples > 1)
2182 } else if (isl_surf_usage_is_depth(surf->usage)) {
2192 } else if (surf->samples > 1) {
2209 if (surf->row_pitch_B % 512 != 0)
2215 if (surf->dim == ISL_SURF_DIM_3D) {
2235 if (surf->tiling != ISL_TILING_Y0 && surf->tiling != ISL_TILING_4 &&
2236 surf->tiling != ISL_TILING_64)
2240 if (surf->samples == 1 && surf->tiling == ISL_TILING_64)
2244 if (surf->samples > 1)
2248 if (isl_surf_usage_is_depth_or_stencil(surf->usage))
2258 if (ISL_GFX_VER(dev) <= 8 && surf->dim != ISL_SURF_DIM_2D)
2276 (surf->levels > 1 || surf->logical_level0_px.array_len > 1))
2285 if (ISL_GFX_VER(dev) >= 9 && !isl_tiling_is_any_y(surf->tiling))
2294 const struct isl_surf *surf,
2299 if (!isl_surf_supports_ccs(dev, surf, hiz_or_mcs_surf))
2304 switch (isl_format_get_layout(surf->format)->bpb) {
2321 .width = isl_surf_get_row_pitch_el(surf),
2322 .height = surf->size_B / surf->row_pitch_B,
2330 assert(!ok || ccs_surf->size_B == surf->size_B / 256);
2335 switch (isl_format_get_layout(surf->format)->bpb) {
2342 } else if (surf->tiling == ISL_TILING_Y0) {
2343 switch (isl_format_get_layout(surf->format)->bpb) {
2349 } else if (surf->tiling == ISL_TILING_X) {
2350 switch (isl_format_get_layout(surf->format)->bpb) {
2361 .dim = surf->dim,
2363 .width = surf->logical_level0_px.width,
2364 .height = surf->logical_level0_px.height,
2365 .depth = surf->logical_level0_px.depth,
2366 .levels = surf->levels,
2367 .array_len = surf->logical_level0_px.array_len,
2428 if (info->surf->dim == ISL_SURF_DIM_3D) {
2430 info->surf->logical_level0_px.depth);
2433 info->surf->logical_level0_px.array_len);
2494 if (info->surf) {
2495 assert((info->surf->usage & ISL_SURF_USAGE_CPB_BIT));
2496 assert(info->surf->dim != ISL_SURF_DIM_3D);
2497 assert(info->surf->tiling == ISL_TILING_4 ||
2498 info->surf->tiling == ISL_TILING_64);
2499 assert(info->surf->format == ISL_FORMAT_R8_UINT);
2510 get_image_offset_sa_gfx4_2d(const struct isl_surf *surf,
2515 assert(level < surf->levels);
2516 if (surf->dim == ISL_SURF_DIM_3D)
2517 assert(logical_array_layer < surf->logical_level0_px.depth);
2519 assert(logical_array_layer < surf->logical_level0_px.array_len);
2522 isl_surf_get_image_alignment_sa(surf);
2524 const uint32_t W0 = surf->phys_level0_sa.width;
2525 const uint32_t H0 = surf->phys_level0_sa.height;
2528 (surf->msaa_layout == ISL_MSAA_LAYOUT_ARRAY ? surf->samples : 1);
2531 uint32_t y = phys_layer * isl_surf_get_array_pitch_sa_rows(surf);
2552 get_image_offset_sa_gfx4_3d(const struct isl_surf *surf,
2557 assert(level < surf->levels);
2558 if (surf->dim == ISL_SURF_DIM_3D) {
2559 assert(surf->phys_level0_sa.array_len == 1);
2560 assert(logical_z_offset_px < isl_minify(surf->phys_level0_sa.depth, level));
2562 assert(surf->dim == ISL_SURF_DIM_2D);
2563 assert(surf->usage & ISL_SURF_USAGE_CUBE_BIT);
2564 assert(surf->phys_level0_sa.array_len == 6);
2565 assert(logical_z_offset_px < surf->phys_level0_sa.array_len);
2569 isl_surf_get_image_alignment_sa(surf);
2571 const uint32_t W0 = surf->phys_level0_sa.width;
2572 const uint32_t H0 = surf->phys_level0_sa.height;
2573 const uint32_t D0 = surf->phys_level0_sa.depth;
2574 const uint32_t AL = surf->phys_level0_sa.array_len;
2582 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, l) : AL,
2592 isl_align_npot(surf->dim == ISL_SURF_DIM_3D ? isl_minify(D0, level) : AL,
2605 get_image_offset_sa_gfx6_stencil_hiz(const struct isl_surf *surf,
2611 assert(level < surf->levels);
2612 assert(surf->logical_level0_px.depth == 1);
2613 assert(logical_array_layer < surf->logical_level0_px.array_len);
2615 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2618 isl_surf_get_image_alignment_sa(surf);
2621 isl_surf_get_tile_info(surf, &tile_info);
2630 const uint32_t W0 = surf->phys_level0_sa.w;
2631 const uint32_t H0 = surf->phys_level0_sa.h;
2639 if (surf->phys_level0_sa.array_len > 1)
2640 assert(surf->array_pitch_el_rows == isl_assert_div(H, fmtl->bh));
2647 const uint32_t h = isl_align(H * surf->phys_level0_sa.a,
2668 get_image_offset_sa_gfx9_1d(const struct isl_surf *surf,
2673 assert(level < surf->levels);
2674 assert(layer < surf->phys_level0_sa.array_len);
2675 assert(surf->phys_level0_sa.height == 1);
2676 assert(surf->phys_level0_sa.depth == 1);
2677 assert(surf->samples == 1);
2679 const uint32_t W0 = surf->phys_level0_sa.width;
2681 isl_surf_get_image_alignment_sa(surf);
2693 *y_offset_sa = layer * isl_surf_get_array_pitch_sa_rows(surf);
2705 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2714 assert(level < surf->levels);
2715 assert(logical_array_layer < surf->logical_level0_px.array_len);
2717 < isl_minify(surf->logical_level0_px.depth, level));
2719 switch (surf->dim_layout) {
2721 get_image_offset_sa_gfx9_1d(surf, level, logical_array_layer,
2727 get_image_offset_sa_gfx4_2d(surf, level, logical_array_layer
2734 get_image_offset_sa_gfx4_3d(surf, level, logical_array_layer +
2741 get_image_offset_sa_gfx6_stencil_hiz(surf, level, logical_array_layer +
2754 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2763 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2765 assert(level < surf->levels);
2766 assert(logical_array_layer < surf->logical_level0_px.array_len);
2768 < isl_minify(surf->logical_level0_px.depth, level));
2771 isl_surf_get_image_offset_sa(surf, level,
2785 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2793 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2796 isl_surf_get_image_offset_B_tile_el(surf, level,
2817 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2825 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2829 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
2837 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2838 surf->msaa_layout, fmtl->bpb,
2839 surf->samples,
2840 surf->row_pitch_B,
2841 surf->array_pitch_el_rows,
2856 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2865 isl_surf_get_image_offset_el(surf, level, logical_array_layer,
2873 const uint32_t subimage_w_sa = isl_minify(surf->phys_level0_sa.w, level);
2874 const uint32_t subimage_h_sa = isl_minify(surf->phys_level0_sa.h, level);
2875 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2888 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2889 surf->msaa_layout, fmtl->bpb,
2890 surf->samples,
2891 surf->row_pitch_B,
2892 surf->array_pitch_el_rows,
2903 isl_tiling_get_intratile_offset_el(surf->tiling, surf->dim,
2904 surf->msaa_layout, fmtl->bpb,
2905 surf->samples,
2906 surf->row_pitch_B,
2907 surf->array_pitch_el_rows,
2923 assert(*end_tile_B <= surf->size_B);
2928 const struct isl_surf *surf,
2937 isl_surf_get_image_offset_B_tile_sa(surf,
2949 surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
2954 .format = surf->format,
2955 .width = isl_minify(surf->logical_level0_px.w, level),
2956 .height = isl_minify(surf->logical_level0_px.h, level),
2960 .samples = surf->samples,
2961 .row_pitch_B = surf->row_pitch_B,
2963 .tiling_flags = (1 << surf->tiling));
2969 const struct isl_surf *surf,
2978 isl_format_get_layout(surf->format);
2982 assert(isl_format_is_compressed(surf->format));
2988 isl_minify(surf->logical_level0_px.width, view->base_level);
2990 isl_minify(surf->logical_level0_px.height, view->base_level);
2992 assert(surf->samples == 1);
3029 *ucompr_surf = *surf;
3040 ucompr_surf->phys_level0_sa = isl_surf_get_phys_level0_el(surf);
3055 isl_surf_get_image_offset_B_tile_el(surf,
3057 surf->dim == ISL_SURF_DIM_3D ?
3059 surf->dim == ISL_SURF_DIM_3D ?
3069 surf->usage & (~ISL_SURF_USAGE_CUBE_BIT);
3081 .row_pitch_B = surf->row_pitch_B,
3083 .tiling_flags = (1 << surf->tiling));
3175 const struct isl_surf *surf)
3187 bool has_stencil = surf->usage & ISL_SURF_USAGE_STENCIL_BIT;
3189 assert(surf->usage & ISL_SURF_USAGE_DEPTH_BIT);
3194 switch (surf->format) {