Lines Matching refs:surf
126 const struct radeon_surf *surf)
151 return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
152 surf->u.gfx9.color.dcc.independent_128B_blocks &&
153 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
155 surf->u.gfx9.color.dcc.independent_64B_blocks &&
156 surf->u.gfx9.color.dcc.independent_128B_blocks &&
157 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
169 ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf,
186 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
187 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
188 surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
631 struct radeon_surf *surf, bool is_stencil, unsigned level,
679 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x;
681 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
685 AddrSurfInfoIn->basePitch *= surf->blk_w;
693 surf_level = is_stencil ? &surf->u.legacy.zs.stencil_level[level] : &surf->u.legacy.level[level];
694 dcc_level = &surf->u.legacy.color.dcc_level[level];
695 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256;
717 surf->u.legacy.zs.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
719 surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
723 surf->prt_tile_width = AddrSurfInfoOut->pitchAlign;
724 surf->prt_tile_height = AddrSurfInfoOut->heightAlign;
725 surf->prt_tile_depth = AddrSurfInfoOut->depthAlign;
727 if (surf_level->nblk_x >= surf->prt_tile_width &&
728 surf_level->nblk_y >= surf->prt_tile_height) {
730 surf->first_mip_tail_level = level + 1;
734 surf->surf_size = (uint64_t)surf_level->offset_256B * 256 + AddrSurfInfoOut->surfSize;
753 dcc_level->dcc_offset = surf->meta_size;
754 surf->num_meta_levels = level + 1;
755 surf->meta_size = dcc_level->dcc_offset + AddrDccOut->dccRamSize;
756 surf->meta_alignment_log2 = MAX2(surf->meta_alignment_log2, util_logbase2(AddrDccOut->dccRamBaseAlign));
779 surf->meta_slice_size = AddrDccOut->dccRamSize / config->info.array_size;
804 if (surf->flags & RADEON_SURF_CONTIGUOUS_DCC_LAYERS &&
805 surf->meta_slice_size != dcc_level->dcc_slice_fast_clear_size) {
806 surf->meta_size = 0;
807 surf->num_meta_levels = 0;
818 level == 0 && !(surf->flags & RADEON_SURF_NO_HTILE)) {
832 surf->meta_size = AddrHtileOut->htileBytes;
833 surf->meta_slice_size = AddrHtileOut->sliceSize;
834 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign);
835 surf->meta_pitch = AddrHtileOut->pitch;
836 surf->num_meta_levels = level + 1;
843 static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, const struct radeon_info *info)
845 uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
848 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
850 surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
853 static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
857 tileb = 8 * 8 * surf->bpe;
858 tileb = MIN2(surf->u.legacy.tile_split, tileb);
867 static bool get_display_flag(const struct ac_surf_config *config, const struct radeon_surf *surf)
870 unsigned bpe = surf->bpe;
876 if (surf->modifier != DRM_FORMAT_MOD_INVALID)
880 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
881 surf->flags & RADEON_SURF_SCANOUT && config->info.samples <= 1 && surf->blk_w <= 2 &&
882 surf->blk_h == 1) {
884 if (surf->blk_w == 2 && surf->blk_h == 1)
906 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *csio, struct radeon_surf *surf)
908 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);
909 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1;
910 gfx6_set_micro_tile_mode(surf, info);
914 surf->u.legacy.bankw = csio->pTileInfo->bankWidth;
915 surf->u.legacy.bankh = csio->pTileInfo->bankHeight;
916 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio;
917 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes;
918 surf->u.legacy.num_banks = csio->pTileInfo->banks;
919 surf->u.legacy.macro_tile_index = csio->macroModeIndex;
921 surf->u.legacy.macro_tile_index = 0;
927 surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
928 !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) &&
929 !get_display_flag(config, surf)) {
947 u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
948 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle;
954 struct radeon_surf *surf)
960 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER || surf->is_linear ||
961 (config->info.samples >= 2 && !surf->fmask_size))
990 unsigned width = align(surf->u.legacy.level[0].nblk_x, cl_width * 8);
991 unsigned height = align(surf->u.legacy.level[0].nblk_y, cl_height * 8);
997 surf->u.legacy.color.cmask_slice_tile_max = (width * height) / (128 * 128);
998 if (surf->u.legacy.color.cmask_slice_tile_max)
999 surf->u.legacy.color.cmask_slice_tile_max -= 1;
1009 surf->cmask_alignment_log2 = util_logbase2(MAX2(256, base_align));
1010 surf->cmask_slice_size = align(slice_bytes, base_align);
1011 surf->cmask_size = surf->cmask_slice_size * num_layers;
1015 * Fill in the tiling information in \p surf based on the given surface config.
1017 * The following fields of \p surf must be initialized by the caller:
1022 struct radeon_surf *surf)
1044 compressed = surf->blk_w == 4 && surf->blk_h == 4;
1051 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) && mode < RADEON_SURF_MODE_1D)
1060 if (surf->flags & RADEON_SURF_PRT)
1066 if (surf->flags & RADEON_SURF_PRT)
1079 switch (surf->bpe) {
1090 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
1096 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)) {
1101 if (surf->flags & RADEON_SURF_SCANOUT)
1103 else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
1108 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1109 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
1111 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
1113 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
1114 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
1121 !(surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE);
1131 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
1135 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
1136 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
1170 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
1171 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw &&
1172 surf->u.legacy.bankh && surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
1175 AddrTileInfoIn.banks = surf->u.legacy.num_banks;
1176 AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
1177 AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
1178 AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
1179 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
1180 AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
1192 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
1197 if (surf->bpe == 2)
1202 if (surf->bpe == 1)
1204 else if (surf->bpe == 2)
1206 else if (surf->bpe == 4)
1219 AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
1223 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
1224 surf->num_meta_levels = 0;
1225 surf->surf_size = 0;
1226 surf->meta_size = 0;
1227 surf->meta_slice_size = 0;
1228 surf->meta_alignment_log2 = 0;
1231 (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER);
1236 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn,
1247 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1258 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1265 if (surf->flags & RADEON_SURF_SBUFFER) {
1272 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
1275 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn,
1282 if (surf->u.legacy.zs.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
1283 surf->u.legacy.stencil_adjusted = true;
1285 surf->u.legacy.level[level].nblk_x = surf->u.legacy.zs.stencil_level[level].nblk_x;
1290 r = gfx6_surface_settings(addrlib, info, config, &AddrSurfInfoOut, surf);
1297 surf->u.legacy.stencil_tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
1305 !(surf->flags & RADEON_SURF_NO_FMASK)) {
1326 surf->fmask_size = fout.fmaskBytes;
1327 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
1328 surf->fmask_slice_size = fout.sliceSize;
1329 surf->fmask_tile_swizzle = 0;
1331 surf->u.legacy.color.fmask.slice_tile_max = (fout.pitch * fout.height) / 64;
1332 if (surf->u.legacy.color.fmask.slice_tile_max)
1333 surf->u.legacy.color.fmask.slice_tile_max -= 1;
1335 surf->u.legacy.color.fmask.tiling_index = fout.tileIndex;
1336 surf->u.legacy.color.fmask.bankh = fout.pTileInfo->bankHeight;
1337 surf->u.legacy.color.fmask.pitch_in_pixels = fout.pitch;
1340 if (config->info.fmask_surf_index && !(surf->flags & RADEON_SURF_SHAREABLE)) {
1358 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1359 surf->fmask_tile_swizzle = xout.tileSwizzle;
1367 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_size && config->info.levels > 1) {
1376 surf->meta_size = align64(surf->surf_size >> 8, (1 << surf->meta_alignment_log2) * 4);
1382 if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_TC_COMPATIBLE_HTILE) &&
1383 surf->meta_size && config->info.levels > 1) {
1385 const unsigned total_pixels = surf->surf_size / surf->bpe;
1389 surf->meta_size = (total_pixels / htile_block_size) * htile_element_size;
1390 surf->meta_size = align(surf->meta_size, 1 << surf->meta_alignment_log2);
1391 } else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && !surf->meta_size) {
1393 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
1396 surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
1397 surf->is_displayable = surf->is_linear || surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY ||
1398 surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER;
1405 if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER) {
1410 ac_compute_cmask(info, config, surf);
1416 struct radeon_surf *surf,
1472 if (surf->flags & RADEON_SURF_FORCE_MICRO_TILE_MODE) {
1475 if (surf->micro_tile_mode == RADEON_MICRO_MODE_DISPLAY)
1477 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_STANDARD)
1479 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_DEPTH)
1481 else if (surf->micro_tile_mode == RADEON_MICRO_MODE_RENDER)
1523 const struct radeon_surf *surf)
1527 return surf->u.gfx9.color.dcc.independent_64B_blocks && !surf->u.gfx9.color.dcc.independent_128B_blocks &&
1528 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1533 return !surf->u.gfx9.color.dcc.independent_64B_blocks && surf->u.gfx9.color.dcc.independent_128B_blocks &&
1534 surf->u.gfx9.color.dcc.max_compressed_block_size <= V_028C78_MAX_BLOCK_SIZE_128B;
1537 bool valid_64b = surf->u.gfx9.color.dcc.independent_64B_blocks &&
1538 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B;
1539 bool valid_128b = surf->u.gfx9.color.dcc.independent_128B_blocks &&
1540 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B;
1546 return surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
1551 return (surf->u.gfx9.color.dcc.independent_64B_blocks != surf->u.gfx9.color.dcc.independent_128B_blocks &&
1553 (surf->u.gfx9.color.dcc.independent_64B_blocks &&
1554 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1592 const struct radeon_surf *surf, bool rb_aligned,
1599 if (surf->bpe != 4)
1617 assert(surf->u.gfx9.color.dcc.independent_64B_blocks &&
1618 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
1624 if (info->gfx_level == GFX10 && surf->u.gfx9.color.dcc.independent_128B_blocks)
1628 (surf->u.gfx9.color.dcc.independent_64B_blocks &&
1629 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B));
1709 const struct ac_surf_config *config, struct radeon_surf *surf,
1724 surf->prt_tile_width = out.blockWidth;
1725 surf->prt_tile_height = out.blockHeight;
1726 surf->prt_tile_depth = out.blockSlices;
1728 surf->first_mip_tail_level = out.firstMipIdInTail;
1731 surf->u.gfx9.prt_level_offset[i] = mip_info[i].macroBlockOffset + mip_info[i].mipTailOffset;
1734 surf->u.gfx9.prt_level_pitch[i] = mip_info[i].pitch;
1736 surf->u.gfx9.prt_level_pitch[i] = out.mipChainPitch;
1741 surf->u.gfx9.zs.stencil_swizzle_mode = in->swizzleMode;
1742 surf->u.gfx9.zs.stencil_epitch =
1744 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign));
1745 surf->u.gfx9.zs.stencil_offset = align(surf->surf_size, out.baseAlign);
1746 surf->surf_size = surf->u.gfx9.zs.stencil_offset + out.surfSize;
1750 surf->u.gfx9.swizzle_mode = in->swizzleMode;
1751 surf->u.gfx9.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : out.mipChainPitch - 1;
1757 surf->u.gfx9.color.fmask_swizzle_mode = surf->u.gfx9.swizzle_mode & ~0x3;
1758 surf->u.gfx9.color.fmask_epitch = surf->u.gfx9.epitch;
1761 surf->u.gfx9.surf_slice_size = out.sliceSize;
1762 surf->u.gfx9.surf_pitch = out.pitch;
1763 surf->u.gfx9.surf_height = out.height;
1764 surf->surf_size = out.surfSize;
1765 surf->surf_alignment_log2 = util_logbase2(out.baseAlign);
1767 if (!compressed && surf->blk_w > 1 && out.pitch == out.pixelPitch &&
1768 surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR) {
1770 surf->u.gfx9.surf_pitch = align(surf->u.gfx9.surf_pitch / surf->blk_w, 256 / surf->bpe);
1771 surf->u.gfx9.epitch =
1772 MAX2(surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch * surf->blk_w - 1);
1773 /* The surface is really a surf->bpe bytes per pixel surface even if we
1774 * use it as a surf->bpe bytes per element one.
1778 surf->u.gfx9.surf_slice_size =
1779 MAX2(surf->u.gfx9.surf_slice_size,
1780 surf->u.gfx9.surf_pitch * out.height * surf->bpe * surf->blk_w);
1781 surf->surf_size = surf->u.gfx9.surf_slice_size * in->numSlices;
1785 int alignment = 256 / surf->bpe;
1787 surf->u.gfx9.offset[i] = mip_info[i].offset;
1789 surf->u.gfx9.pitch[i] = align(mip_info[i].pitch / surf->blk_w, alignment);
1793 surf->u.gfx9.base_mip_width = mip_info[0].pitch;
1794 surf->u.gfx9.base_mip_height = mip_info[0].height;
1799 if (surf->flags & RADEON_SURF_NO_HTILE)
1828 surf->meta_size = hout.htileBytes;
1829 surf->meta_slice_size = hout.sliceSize;
1830 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign);
1831 surf->meta_pitch = hout.pitch;
1832 surf->num_meta_levels = in->numMipLevels;
1835 surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset;
1836 surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize;
1842 surf->num_meta_levels = i + 1;
1847 if (!surf->num_meta_levels)
1848 surf->meta_size = 0;
1851 ac_copy_htile_equation(info, &hout, &surf->u.gfx9.zs.htile_equation);
1860 !(surf->flags & RADEON_SURF_SHAREABLE) && !in->flags.display) {
1879 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8));
1880 surf->tile_swizzle = xout.pipeBankXor;
1884 if (surf->modifier != DRM_FORMAT_MOD_INVALID) {
1885 use_dcc = ac_modifier_has_dcc(surf->modifier);
1887 use_dcc = info->has_graphics && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed &&
1890 is_dcc_supported_by_DCN(info, config, surf, !in->flags.metaRbUnaligned,
1926 surf->u.gfx9.color.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1927 surf->u.gfx9.color.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1928 surf->u.gfx9.color.dcc_block_width = dout.compressBlkWidth;
1929 surf->u.gfx9.color.dcc_block_height = dout.compressBlkHeight;
1930 surf->u.gfx9.color.dcc_block_depth = dout.compressBlkDepth;
1931 surf->u.gfx9.color.dcc_pitch_max = dout.pitch - 1;
1932 surf->u.gfx9.color.dcc_height = dout.height;
1933 surf->meta_size = dout.dccRamSize;
1934 surf->meta_slice_size = dout.dccRamSliceSize;
1935 surf->meta_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
1936 surf->num_meta_levels = in->numMipLevels;
1961 surf->u.gfx9.meta_levels[i].offset = meta_mip_info[i].offset;
1962 surf->u.gfx9.meta_levels[i].size = meta_mip_info[i].sliceSize;
1972 surf->num_meta_levels = i + 1;
1974 surf->num_meta_levels = i;
1979 if (!surf->num_meta_levels)
1980 surf->meta_size = 0;
1982 surf->u.gfx9.color.display_dcc_size = surf->meta_size;
1983 surf->u.gfx9.color.display_dcc_alignment_log2 = surf->meta_alignment_log2;
1984 surf->u.gfx9.color.display_dcc_pitch_max = surf->u.gfx9.color.dcc_pitch_max;
1985 surf->u.gfx9.color.display_dcc_height = surf->u.gfx9.color.dcc_height;
1988 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.dcc_equation);
1992 ac_modifier_has_dcc_retile(surf->modifier)) && surf->num_meta_levels) {
2000 assert(surf->tile_swizzle == 0);
2001 assert(surf->u.gfx9.color.dcc.pipe_aligned || surf->u.gfx9.color.dcc.rb_aligned);
2012 surf->u.gfx9.color.display_dcc_size = dout.dccRamSize;
2013 surf->u.gfx9.color.display_dcc_alignment_log2 = util_logbase2(dout.dccRamBaseAlign);
2014 surf->u.gfx9.color.display_dcc_pitch_max = dout.pitch - 1;
2015 surf->u.gfx9.color.display_dcc_height = dout.height;
2016 assert(surf->u.gfx9.color.display_dcc_size <= surf->meta_size);
2018 ac_copy_dcc_equation(info, &dout, &surf->u.gfx9.color.display_dcc_equation);
2019 surf->u.gfx9.color.dcc.display_equation_valid = true;
2025 in->numSamples > 1 && !(surf->flags & RADEON_SURF_NO_FMASK)) {
2032 ret = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, in, true, &fin.swizzleMode);
2046 surf->u.gfx9.color.fmask_swizzle_mode = fin.swizzleMode;
2047 surf->u.gfx9.color.fmask_epitch = fout.pitch - 1;
2048 surf->fmask_size = fout.fmaskBytes;
2049 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
2050 surf->fmask_slice_size = fout.sliceSize;
2054 !(surf->flags & RADEON_SURF_SHAREABLE)) {
2074 assert(xout.pipeBankXor <= u_bit_consecutive(0, sizeof(surf->fmask_tile_swizzle) * 8));
2075 surf->fmask_tile_swizzle = xout.pipeBankXor;
2084 (surf->fmask_size && in->numSamples >= 2))) {
2106 cin.swizzleMode = surf->u.gfx9.color.fmask_swizzle_mode;
2119 surf->cmask_size = cout.cmaskBytes;
2120 surf->cmask_alignment_log2 = util_logbase2(cout.baseAlign);
2121 surf->cmask_slice_size = cout.sliceSize;
2122 surf->cmask_pitch = cout.pitch;
2123 surf->cmask_height = cout.height;
2124 surf->u.gfx9.color.cmask_level0.offset = meta_mip_info[0].offset;
2125 surf->u.gfx9.color.cmask_level0.size = meta_mip_info[0].sliceSize;
2127 ac_copy_cmask_equation(info, &cout, &surf->u.gfx9.color.cmask_equation);
2136 struct radeon_surf *surf)
2144 compressed = surf->blk_w == 4 && surf->blk_h == 4;
2149 switch (surf->bpe) {
2160 switch (surf->bpe) {
2162 assert(!(surf->flags & RADEON_SURF_ZBUFFER));
2166 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
2170 assert(surf->flags & RADEON_SURF_ZBUFFER || !(surf->flags & RADEON_SURF_SBUFFER));
2174 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2178 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2182 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2188 AddrSurfInfoIn.bpp = surf->bpe * 8;
2191 bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
2192 AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
2193 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
2194 AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
2196 AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
2198 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0;
2204 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER))
2231 if (ac_modifier_has_dcc(surf->modifier)) {
2232 ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn);
2236 if (!(surf->flags & RADEON_SURF_IMPORTED)) {
2238 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2239 surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2240 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2242 surf->u.gfx9.color.dcc.independent_64B_blocks = 0;
2243 surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2244 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2263 if (!(surf->flags & RADEON_SURF_IMPORTED) &&
2269 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2270 surf->u.gfx9.color.dcc.independent_128B_blocks = 0;
2271 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2281 surf->u.gfx9.color.dcc.independent_64B_blocks = 1;
2282 surf->u.gfx9.color.dcc.independent_128B_blocks = 1;
2283 surf->u.gfx9.color.dcc.max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2289 if (surf->modifier == DRM_FORMAT_MOD_INVALID) {
2293 assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
2299 if (surf->flags & RADEON_SURF_IMPORTED ||
2300 (info->gfx_level >= GFX10 && surf->flags & RADEON_SURF_FORCE_SWIZZLE_MODE)) {
2301 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode;
2305 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2318 assert(!ac_modifier_has_dcc(surf->modifier) ||
2319 !(surf->flags & RADEON_SURF_DISABLE_DCC));
2321 AddrSurfInfoIn.swizzleMode = ac_modifier_gfx9_swizzle_mode(surf->modifier);
2324 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
2325 surf->has_stencil = !!(surf->flags & RADEON_SURF_SBUFFER);
2327 surf->num_meta_levels = 0;
2328 surf->surf_size = 0;
2329 surf->fmask_size = 0;
2330 surf->meta_size = 0;
2331 surf->meta_slice_size = 0;
2332 surf->u.gfx9.surf_offset = 0;
2334 surf->u.gfx9.zs.stencil_offset = 0;
2335 surf->cmask_size = 0;
2338 (surf->flags & RADEON_SURF_SBUFFER) && !(surf->flags & RADEON_SURF_ZBUFFER);
2342 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2348 if (surf->flags & RADEON_SURF_SBUFFER) {
2354 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false,
2361 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn);
2366 surf->is_linear = surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR;
2372 r = Addr2IsValidDisplaySwizzleMode(addrlib->handle, surf->u.gfx9.swizzle_mode,
2373 surf->bpe * 8, &displayable);
2378 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
2379 surf->num_meta_levels &&
2380 (!is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2381 surf->u.gfx9.color.dcc.pipe_aligned) ||
2383 (info->use_display_dcc_with_retile_blit && !surf->u.gfx9.color.dcc.display_equation_valid)))
2386 surf->is_displayable = displayable;
2389 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable);
2392 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->num_meta_levels) {
2393 assert(is_dcc_supported_by_L2(info, surf));
2395 assert(is_dcc_supported_by_CB(info, surf->u.gfx9.swizzle_mode));
2396 if (AddrSurfInfoIn.flags.display && surf->modifier == DRM_FORMAT_MOD_INVALID) {
2397 assert(is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2398 surf->u.gfx9.color.dcc.pipe_aligned));
2403 AddrSurfInfoIn.flags.color && !surf->is_linear &&
2404 (1 << surf->surf_alignment_log2) >= 64 * 1024 && /* 64KB tiling */
2405 !(surf->flags & (RADEON_SURF_DISABLE_DCC | RADEON_SURF_FORCE_SWIZZLE_MODE |
2407 surf->modifier == DRM_FORMAT_MOD_INVALID &&
2408 is_dcc_supported_by_DCN(info, config, surf, surf->u.gfx9.color.dcc.rb_aligned,
2409 surf->u.gfx9.color.dcc.pipe_aligned)) {
2412 AddrSurfInfoIn.flags.display && surf->bpe == 4) {
2413 assert(surf->num_meta_levels);
2418 assert(surf->num_meta_levels);
2421 if (!surf->meta_size) {
2423 surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
2426 if (surf->modifier != DRM_FORMAT_MOD_INVALID) {
2427 assert((surf->num_meta_levels != 0) == ac_modifier_has_dcc(surf->modifier));
2430 switch (surf->u.gfx9.swizzle_mode) {
2439 surf->micro_tile_mode = RADEON_MICRO_MODE_STANDARD;
2451 surf->micro_tile_mode = RADEON_MICRO_MODE_DISPLAY;
2467 surf->micro_tile_mode = RADEON_MICRO_MODE_RENDER;
2477 surf->micro_tile_mode = RADEON_MICRO_MODE_DEPTH;
2489 struct radeon_surf *surf)
2493 r = surf_config_sanity(config, surf->flags);
2498 r = gfx9_compute_surface(addrlib, info, config, mode, surf);
2500 r = gfx6_compute_surface(addrlib->handle, info, config, mode, surf);
2506 surf->total_size = surf->surf_size;
2507 surf->alignment_log2 = surf->surf_alignment_log2;
2510 surf->meta_offset = surf->display_dcc_offset = surf->fmask_offset = surf->cmask_offset = 0;
2512 if (surf->fmask_size) {
2514 surf->fmask_offset = align64(surf->total_size, 1 << surf->fmask_alignment_log2);
2515 surf->total_size = surf->fmask_offset + surf->fmask_size;
2516 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->fmask_alignment_log2);
2520 if (surf->cmask_size && config->info.samples >= 2) {
2521 surf->cmask_offset = align64(surf->total_size, 1 << surf->cmask_alignment_log2);
2522 surf->total_size = surf->cmask_offset + surf->cmask_size;
2523 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->cmask_alignment_log2);
2526 if (surf->is_displayable)
2527 surf->flags |= RADEON_SURF_SCANOUT;
2529 if (surf->meta_size &&
2531 (info->gfx_level >= GFX9 || !get_display_flag(config, surf))) {
2536 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
2537 surf->u.gfx9.color.dcc.display_equation_valid) {
2539 surf->display_dcc_offset = align64(surf->total_size, 1 << surf->u.gfx9.color.display_dcc_alignment_log2);
2540 surf->total_size = surf->display_dcc_offset + surf->u.gfx9.color.display_dcc_size;
2543 surf->meta_offset = align64(surf->total_size, 1 << surf->meta_alignment_log2);
2544 surf->total_size = surf->meta_offset + surf->meta_size;
2545 surf->alignment_log2 = MAX2(surf->alignment_log2, surf->meta_alignment_log2);
2552 void ac_surface_zero_dcc_fields(struct radeon_surf *surf)
2554 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
2557 surf->meta_offset = 0;
2558 surf->display_dcc_offset = 0;
2559 if (!surf->fmask_offset && !surf->cmask_offset) {
2560 surf->total_size = surf->surf_size;
2561 surf->alignment_log2 = surf->surf_alignment_log2;
2619 void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2625 surf->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2626 surf->u.gfx9.color.dcc.independent_64B_blocks =
2628 surf->u.gfx9.color.dcc.independent_128B_blocks =
2630 surf->u.gfx9.color.dcc.max_compressed_block_size =
2632 surf->u.gfx9.color.display_dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
2635 surf->u.gfx9.swizzle_mode > 0 ? RADEON_SURF_MODE_2D : RADEON_SURF_MODE_LINEAR_ALIGNED;
2637 surf->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2638 surf->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2639 surf->u.legacy.bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2640 surf->u.legacy.tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
2641 surf->u.legacy.mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2642 surf->u.legacy.num_banks = 2 << AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2654 surf->flags |= RADEON_SURF_SCANOUT;
2656 surf->flags &= ~RADEON_SURF_SCANOUT;
2659 void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2667 if (surf->meta_offset) {
2668 dcc_offset = surf->display_dcc_offset ? surf->display_dcc_offset : surf->meta_offset;
2672 *tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, surf->u.gfx9.swizzle_mode);
2674 *tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, surf->u.gfx9.color.display_dcc_pitch_max);
2676 AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, surf->u.gfx9.color.dcc.independent_64B_blocks);
2678 AMDGPU_TILING_SET(DCC_INDEPENDENT_128B, surf->u.gfx9.color.dcc.independent_128B_blocks);
2680 surf->u.gfx9.color.dcc.max_compressed_block_size);
2681 *tiling_flags |= AMDGPU_TILING_SET(SCANOUT, (surf->flags & RADEON_SURF_SCANOUT) != 0);
2683 if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D)
2685 else if (surf->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D)
2690 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, surf->u.legacy.pipe_config);
2691 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(surf->u.legacy.bankw));
2692 *tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(surf->u.legacy.bankh));
2693 if (surf->u.legacy.tile_split)
2695 AMDGPU_TILING_SET(TILE_SPLIT, eg_tile_split_rev(surf->u.legacy.tile_split));
2696 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(surf->u.legacy.mtilea));
2697 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, util_logbase2(surf->u.legacy.num_banks) - 1);
2699 if (surf->flags & RADEON_SURF_SCANOUT)
2712 bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2719 if (surf->modifier != DRM_FORMAT_MOD_INVALID)
2723 offset = surf->u.gfx9.surf_offset;
2725 offset = (uint64_t)surf->u.legacy.level[0].offset_256B * 256;
2732 ac_surface_zero_dcc_fields(surf);
2768 surf->meta_offset = (uint64_t)desc[7] << 8;
2772 surf->meta_offset =
2774 surf->u.gfx9.color.dcc.pipe_aligned = G_008F24_META_PIPE_ALIGNED(desc[5]);
2775 surf->u.gfx9.color.dcc.rb_aligned = G_008F24_META_RB_ALIGNED(desc[5]);
2778 if (!surf->u.gfx9.color.dcc.pipe_aligned && !surf->u.gfx9.color.dcc.rb_aligned)
2779 assert(surf->is_displayable);
2785 surf->meta_offset =
2787 surf->u.gfx9.color.dcc.pipe_aligned = G_00A018_META_PIPE_ALIGNED(desc[6]);
2798 ac_surface_zero_dcc_fields(surf);
2804 void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf,
2817 desc[7] = surf->meta_offset >> 8;
2820 desc[7] = surf->meta_offset >> 8;
2822 desc[5] |= S_008F24_META_DATA_ADDRESS(surf->meta_offset >> 40);
2828 desc[6] |= S_00A018_META_DATA_ADDRESS_LO(surf->meta_offset >> 8);
2829 desc[7] = surf->meta_offset >> 16;
2857 metadata[10 + i] = surf->u.legacy.level[i].offset_256B;
2863 static uint32_t ac_surface_get_gfx9_pitch_align(struct radeon_surf *surf)
2865 if (surf->u.gfx9.swizzle_mode == ADDR_SW_LINEAR)
2866 return 256 / surf->bpe;
2868 if (surf->u.gfx9.resource_type == RADEON_RESOURCE_3D)
2871 unsigned bpe_shift = util_logbase2(surf->bpe) / 2;
2872 switch(surf->u.gfx9.swizzle_mode & ~3) {
2889 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf,
2898 bool require_equal_pitch = surf->surf_size != surf->total_size ||
2904 if (surf->u.gfx9.surf_pitch != pitch && require_equal_pitch)
2907 if ((ac_surface_get_gfx9_pitch_align(surf) - 1) & pitch)
2910 if (pitch != surf->u.gfx9.surf_pitch) {
2911 unsigned slices = surf->surf_size / surf->u.gfx9.surf_slice_size;
2913 surf->u.gfx9.surf_pitch = pitch;
2914 surf->u.gfx9.epitch = pitch - 1;
2915 surf->u.gfx9.surf_slice_size = (uint64_t)pitch * surf->u.gfx9.surf_height * surf->bpe;
2916 surf->total_size = surf->surf_size = surf->u.gfx9.surf_slice_size * slices;
2919 surf->u.gfx9.surf_offset = offset;
2920 if (surf->u.gfx9.zs.stencil_offset)
2921 surf->u.gfx9.zs.stencil_offset += offset;
2924 if (surf->u.legacy.level[0].nblk_x != pitch && require_equal_pitch)
2927 surf->u.legacy.level[0].nblk_x = pitch;
2928 surf->u.legacy.level[0].slice_size_dw =
2929 ((uint64_t)pitch * surf->u.legacy.level[0].nblk_y * surf->bpe) / 4;
2933 for (unsigned i = 0; i < ARRAY_SIZE(surf->u.legacy.level); ++i)
2934 surf->u.legacy.level[i].offset_256B += offset / 256;
2938 if (offset & ((1 << surf->alignment_log2) - 1) ||
2939 offset >= UINT64_MAX - surf->total_size)
2942 if (surf->meta_offset)
2943 surf->meta_offset += offset;
2944 if (surf->fmask_offset)
2945 surf->fmask_offset += offset;
2946 if (surf->cmask_offset)
2947 surf->cmask_offset += offset;
2948 if (surf->display_dcc_offset)
2949 surf->display_dcc_offset += offset;
2953 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf)
2955 if (surf->modifier == DRM_FORMAT_MOD_INVALID)
2957 else if (surf->display_dcc_offset)
2959 else if (surf->meta_offset)
2966 const struct radeon_surf *surf,
2972 return surf->u.gfx9.surf_offset +
2973 layer * surf->u.gfx9.surf_slice_size;
2975 return (uint64_t)surf->u.legacy.level[0].offset_256B * 256 +
2976 layer * (uint64_t)surf->u.legacy.level[0].slice_size_dw * 4;
2980 return surf->display_dcc_offset ?
2981 surf->display_dcc_offset : surf->meta_offset;
2984 return surf->meta_offset;
2991 const struct radeon_surf *surf,
2997 return (surf->is_linear ? surf->u.gfx9.pitch[level] : surf->u.gfx9.surf_pitch) * surf->bpe;
2999 return surf->u.legacy.level[level].nblk_x * surf->bpe;
3002 return 1 + (surf->display_dcc_offset ?
3003 surf->u.gfx9.color.display_dcc_pitch_max : surf->u.gfx9.color.dcc_pitch_max);
3005 return surf->u.gfx9.color.dcc_pitch_max + 1;
3011 uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf,
3016 return surf->surf_size;
3018 return surf->display_dcc_offset ?
3019 surf->u.gfx9.color.display_dcc_size : surf->meta_size;
3021 return surf->meta_size;
3028 const struct radeon_surf *surf)
3035 surf->surf_size, surf->u.gfx9.surf_slice_size,
3036 1 << surf->surf_alignment_log2, surf->u.gfx9.swizzle_mode,
3037 surf->u.gfx9.epitch, surf->u.gfx9.surf_pitch,
3038 surf->blk_w, surf->blk_h, surf->bpe, surf->flags);
3040 if (surf->fmask_offset)
3044 surf->fmask_offset, surf->fmask_size,
3045 1 << surf->fmask_alignment_log2, surf->u.gfx9.color.fmask_swizzle_mode,
3046 surf->u.gfx9.color.fmask_epitch);
3048 if (surf->cmask_offset)
3052 surf->cmask_offset, surf->cmask_size,
3053 1 << surf->cmask_alignment_log2);
3055 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && surf->meta_offset)
3058 surf->meta_offset, surf->meta_size,
3059 1 << surf->meta_alignment_log2);
3061 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_offset)
3065 surf->meta_offset, surf->meta_size, 1 << surf->meta_alignment_log2,
3066 surf->u.gfx9.color.display_dcc_pitch_max, surf->num_meta_levels);
3068 if (surf->has_stencil)
3071 surf->u.gfx9.zs.stencil_offset,
3072 surf->u.gfx9.zs.stencil_swizzle_mode,
3073 surf->u.gfx9.zs.stencil_epitch);
3078 surf->surf_size, 1 << surf->surf_alignment_log2, surf->blk_w,
3079 surf->blk_h, surf->bpe, surf->flags);
3084 surf->surf_size, 1 << surf->surf_alignment_log2,
3085 surf->u.legacy.bankw, surf->u.legacy.bankh,
3086 surf->u.legacy.num_banks, surf->u.legacy.mtilea,
3087 surf->u.legacy.tile_split, surf->u.legacy.pipe_config,
3088 (surf->flags & RADEON_SURF_SCANOUT) != 0);
3090 if (surf->fmask_offset)
3095 surf->fmask_offset, surf->fmask_size,
3096 1 << surf->fmask_alignment_log2, surf->u.legacy.color.fmask.pitch_in_pixels,
3097 surf->u.legacy.color.fmask.bankh,
3098 surf->u.legacy.color.fmask.slice_tile_max,
3099 surf->u.legacy.color.fmask.tiling_index);
3101 if (surf->cmask_offset)
3105 surf->cmask_offset, surf->cmask_size,
3106 1 << surf->cmask_alignment_log2, surf->u.legacy.color.cmask_slice_tile_max);
3108 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER && surf->meta_offset)
3110 surf->meta_offset, surf->meta_size,
3111 1 << surf->meta_alignment_log2);
3113 if (!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && surf->meta_offset)
3115 surf->meta_offset, surf->meta_size, 1 << surf->meta_alignment_log2);
3117 if (surf->has_stencil)
3119 surf->u.legacy.stencil_tile_split);