Lines Matching refs:surf
96 struct radeon_surface *surf);
98 struct radeon_surface *surf);
167 static void surf_minify(struct radeon_surface *surf,
173 surflevel->npix_x = mip_minify(surf->npix_x, level);
174 surflevel->npix_y = mip_minify(surf->npix_y, level);
175 surflevel->npix_z = mip_minify(surf->npix_z, level);
176 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
177 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
178 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
179 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
180 !(surf->flags & RADEON_SURF_FMASK)) {
191 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
194 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
267 struct radeon_surface *surf,
275 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
280 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe);
283 if (surf->flags & RADEON_SURF_SCANOUT) {
284 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
288 for (i = start_level; i <= surf->last_level; i++) {
289 surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
290 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
292 offset = surf->bo_size;
294 offset = ALIGN(offset, surf->bo_alignment);
301 struct radeon_surface *surf,
309 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
311 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe);
316 for (i = start_level; i <= surf->last_level; i++) {
317 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
318 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
320 offset = surf->bo_size;
322 offset = ALIGN(offset, surf->bo_alignment);
329 struct radeon_surface *surf,
337 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples);
341 if (surf->flags & RADEON_SURF_SCANOUT) {
342 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
345 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
349 for (i = start_level; i <= surf->last_level; i++) {
350 surf->level[i].mode = RADEON_SURF_MODE_1D;
351 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
353 offset = surf->bo_size;
355 offset = ALIGN(offset, surf->bo_alignment);
362 struct radeon_surface *surf,
372 (tilew * surf->bpe * surf->nsamples);
374 if (surf->flags & RADEON_SURF_FMASK)
377 if (surf->flags & RADEON_SURF_SCANOUT) {
378 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
381 surf->bo_alignment =
384 surf->nsamples * surf->bpe * 64,
385 xalign * yalign * surf->nsamples * surf->bpe);
389 for (i = start_level; i <= surf->last_level; i++) {
390 surf->level[i].mode = RADEON_SURF_MODE_2D;
391 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset);
392 if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
393 return r6_surface_init_1d(surf_man, surf, offset, i);
396 offset = surf->bo_size;
398 offset = ALIGN(offset, surf->bo_alignment);
405 struct radeon_surface *surf)
411 if (surf->nsamples > 1) {
412 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
413 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
417 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
419 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
427 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
428 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
435 if (surf->nsamples > 1) {
440 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
441 surf->flags |= RADEON_SURF_SET(mode, MODE);
445 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) {
450 if (surf->last_level > 14) {
457 r = r6_surface_init_linear(surf_man, surf, 0, 0);
460 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
463 r = r6_surface_init_1d(surf_man, surf, 0, 0);
466 r = r6_surface_init_2d(surf_man, surf, 0, 0);
475 struct radeon_surface *surf)
570 static void eg_surf_minify(struct radeon_surface *surf,
582 surflevel->npix_x = mip_minify(surf->npix_x, level);
583 surflevel->npix_y = mip_minify(surf->npix_y, level);
584 surflevel->npix_z = mip_minify(surf->npix_z, level);
585 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
586 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
587 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
588 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
589 !(surf->flags & RADEON_SURF_FMASK)) {
605 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
608 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
612 struct radeon_surface *surf,
622 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
626 if (surf->flags & RADEON_SURF_SCANOUT) {
632 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
640 for (i = start_level; i <= surf->last_level; i++) {
642 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
644 offset = surf->bo_size;
646 offset = ALIGN(offset, surf->bo_alignment);
653 struct radeon_surface *surf,
666 tileb = tilew * tileh * bpe * surf->nsamples;
675 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
676 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea;
682 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
690 for (i = start_level; i <= surf->last_level; i++) {
692 eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset);
694 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
697 offset = surf->bo_size;
699 offset = ALIGN(offset, surf->bo_alignment);
706 struct radeon_surface *surf,
712 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
717 if (surf->last_level > 15) {
723 if (surf->nsamples > 1) {
728 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
729 surf->flags |= RADEON_SURF_SET(mode, MODE);
734 switch (surf->tile_split) {
746 switch (surf->mtilea) {
756 if (surf_man->hw_info.num_banks < surf->mtilea) {
760 switch (surf->bankw) {
770 switch (surf->bankh) {
779 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
780 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
789 struct radeon_surface *surf)
792 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
796 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;
798 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
803 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
804 surf->bo_size, 0);
805 surf->stencil_offset = stencil_level[0].offset;
811 struct radeon_surface *surf)
814 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
818 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp;
820 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
821 surf->tile_split, 0, 0);
826 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
827 surf->stencil_tile_split, surf->bo_size, 0);
828 surf->stencil_offset = stencil_level[0].offset;
834 struct radeon_surface *surf)
840 if (surf->nsamples > 1) {
841 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
842 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
846 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
848 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
856 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
857 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
862 r = eg_surface_sanity(surf_man, surf, mode);
867 surf->stencil_offset = 0;
868 surf->bo_alignment = 0;
873 r = r6_surface_init_linear(surf_man, surf, 0, 0);
876 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
879 r = eg_surface_init_1d_miptrees(surf_man, surf);
882 r = eg_surface_init_2d_miptrees(surf_man, surf);
909 struct radeon_surface *surf)
915 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
918 surf->tile_split = 1024;
919 surf->bankw = 1;
920 surf->bankh = 1;
921 surf->mtilea = surf_man->hw_info.num_banks;
922 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
923 for (; surf->bankh <= 8; surf->bankh *= 2) {
924 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
928 if (surf->mtilea > 8) {
929 surf->mtilea = 8;
932 r = eg_surface_sanity(surf_man, surf, mode);
943 if (surf->nsamples > 1) {
944 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
945 switch (surf->nsamples) {
947 surf->tile_split = 128;
950 surf->tile_split = 128;
953 surf->tile_split = 256;
956 surf->tile_split = 512;
960 surf->nsamples, __LINE__);
963 surf->stencil_tile_split = 64;
968 surf->tile_split = MAX2(2 * surf->bpe * 64, 256);
969 if (surf->tile_split > 4096)
970 surf->tile_split = 4096;
974 surf->tile_split = surf_man->hw_info.row_size;
975 surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
986 if (surf->flags & RADEON_SURF_SBUFFER) {
990 tileb = MIN2(surf->tile_split, 64 * surf->nsamples);
992 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples);
998 surf->bankw = 1;
1001 surf->bankh = 4;
1005 surf->bankh = 2;
1008 surf->bankh = 1;
1012 for (; surf->bankh <= 8; surf->bankh *= 2) {
1013 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
1018 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) /
1019 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16;
1020 surf->mtilea = 1 << (log2_int(h_over_w) >> 1);
1287 struct radeon_surface *surf,
1293 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
1298 if (surf->last_level > 15) {
1304 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
1305 if (surf->nsamples > 1) {
1310 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1311 surf->flags |= RADEON_SURF_SET(mode, MODE);
1314 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
1318 if (!surf->tile_split) {
1320 surf->mtilea = 1;
1321 surf->bankw = 1;
1322 surf->bankh = 1;
1323 surf->tile_split = 64;
1324 surf->stencil_tile_split = 64;
1329 if (surf->flags & RADEON_SURF_SBUFFER) {
1330 switch (surf->nsamples) {
1348 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
1350 if (surf->flags & RADEON_SURF_ZBUFFER) {
1351 switch (surf->nsamples) {
1367 } else if (surf->flags & RADEON_SURF_SCANOUT) {
1368 switch (surf->bpe) {
1379 switch (surf->bpe) {
1399 si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_split);
1402 if (surf->flags & RADEON_SURF_SBUFFER) {
1405 if (surf->flags & RADEON_SURF_ZBUFFER) {
1407 } else if (surf->flags & RADEON_SURF_SCANOUT) {
1421 static void si_surf_minify(struct radeon_surface *surf,
1428 surflevel->npix_x = surf->npix_x;
1430 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1432 surflevel->npix_y = mip_minify(surf->npix_y, level);
1433 surflevel->npix_z = mip_minify(surf->npix_z, level);
1435 if (level == 0 && surf->last_level > 0) {
1436 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;
1437 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;
1438 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;
1440 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
1441 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
1442 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
1450 if (level == 0 && surf->last_level == 0)
1452 /* Using just bpe here breaks stencil blitting; surf->bpe works. */
1453 xalign = MAX2(xalign, slice_align / surf->bpe);
1462 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1466 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1469 static void si_surf_minify_2d(struct radeon_surface *surf,
1478 surflevel->npix_x = surf->npix_x;
1480 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level);
1482 surflevel->npix_y = mip_minify(surf->npix_y, level);
1483 surflevel->npix_z = mip_minify(surf->npix_z, level);
1485 if (level == 0 && surf->last_level > 0) {
1486 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w;
1487 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h;
1488 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d;
1490 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
1491 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
1492 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
1495 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D &&
1496 !(surf->flags & RADEON_SURF_FMASK)) {
1511 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
1514 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
1518 struct radeon_surface *surf,
1527 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
1529 xalign = MAX2(8, 64 / surf->bpe);
1532 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes);
1535 for (i = start_level; i <= surf->last_level; i++) {
1536 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
1537 si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset);
1539 offset = surf->bo_size;
1541 offset = ALIGN(offset, surf->bo_alignment);
1543 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1544 surf->tiling_index[i] = tile_mode;
1551 struct radeon_surface *surf,
1565 if (surf->flags & RADEON_SURF_SCANOUT) {
1570 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
1578 for (i = start_level; i <= surf->last_level; i++) {
1580 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset);
1582 offset = surf->bo_size;
1586 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1587 if (surf->level == level) {
1588 surf->tiling_index[i] = tile_mode;
1590 surf->stencil_tiling_index[i] = tile_mode;
1592 surf->stencil_tiling_index[i] = tile_mode;
1600 struct radeon_surface *surf,
1605 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0);
1610 if (surf->flags & RADEON_SURF_SBUFFER) {
1611 r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0);
1612 surf->stencil_offset = surf->stencil_level[0].offset;
1618 struct radeon_surface *surf,
1635 tileb = tilew * tileh * bpe * surf->nsamples;
1644 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea;
1645 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea;
1652 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
1660 for (i = start_level; i <= surf->last_level; i++) {
1662 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
1681 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
1684 aligned_offset = offset = surf->bo_size;
1686 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
1688 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
1689 if (surf->level == level) {
1690 surf->tiling_index[i] = tile_mode;
1692 surf->stencil_tiling_index[i] = tile_mode;
1694 surf->stencil_tiling_index[i] = tile_mode;
1702 struct radeon_surface *surf,
1713 r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, surf->tile_split, 0, 0);
1718 if (surf->flags & RADEON_SURF_SBUFFER) {
1719 r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, surf->stencil_tile_split, surf->bo_size, 0);
1720 surf->stencil_offset = surf->stencil_level[0].offset;
1726 struct radeon_surface *surf)
1732 if (surf->nsamples > 1) {
1733 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1734 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
1738 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1740 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
1748 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1749 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1754 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
1759 surf->stencil_offset = 0;
1760 surf->bo_alignment = 0;
1765 r = r6_surface_init_linear(surf_man, surf, 0, 0);
1768 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
1771 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1774 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
1786 struct radeon_surface *surf)
1791 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
1793 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) &&
1794 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) {
1796 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
1797 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
1800 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2117 struct radeon_surface *surf,
2121 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) {
2126 if (surf->last_level > 15) {
2132 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) {
2133 if (surf->nsamples > 1) {
2138 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2139 surf->flags |= RADEON_SURF_SET(mode, MODE);
2142 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) {
2146 if (!surf->tile_split) {
2148 surf->mtilea = 1;
2149 surf->bankw = 1;
2150 surf->bankh = 1;
2151 surf->tile_split = 64;
2152 surf->stencil_tile_split = 64;
2157 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) {
2158 switch (surf->nsamples) {
2173 if (surf->flags & RADEON_SURF_SBUFFER) {
2176 cik_get_2d_params(surf_man, 1, surf->nsamples, false,
2178 &surf->stencil_tile_split,
2181 } else if (surf->flags & RADEON_SURF_SCANOUT) {
2188 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2189 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode,
2190 NULL, &surf->tile_split, NULL, &surf->mtilea,
2191 &surf->bankw, &surf->bankh);
2195 if (surf->flags & RADEON_SURF_SBUFFER) {
2198 if (surf->flags & RADEON_SURF_ZBUFFER) {
2200 } else if (surf->flags & RADEON_SURF_SCANOUT) {
2215 struct radeon_surface *surf,
2236 tileb = surf->nsamples * tileb_1x;
2246 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea;
2247 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea;
2254 surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
2262 for (i = start_level; i <= surf->last_level; i++) {
2264 si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset);
2283 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i);
2286 aligned_offset = offset = surf->bo_size;
2288 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment);
2290 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) {
2291 if (surf->level == level) {
2292 surf->tiling_index[i] = tile_mode;
2294 surf->stencil_tiling_index[i] = tile_mode;
2296 surf->stencil_tiling_index[i] = tile_mode;
2304 struct radeon_surface *surf,
2310 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples,
2311 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode,
2314 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode,
2315 surf->tile_split, num_pipes, num_banks, 0, 0);
2320 if (surf->flags & RADEON_SURF_SBUFFER) {
2321 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode,
2322 surf->stencil_tile_split, num_pipes, num_banks,
2323 surf->bo_size, 0);
2324 surf->stencil_offset = surf->stencil_level[0].offset;
2330 struct radeon_surface *surf)
2336 if (surf->nsamples > 1) {
2337 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2338 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
2342 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2344 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
2352 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2353 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2358 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2363 surf->stencil_offset = 0;
2364 surf->bo_alignment = 0;
2369 r = r6_surface_init_linear(surf_man, surf, 0, 0);
2372 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0);
2375 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2378 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode);
2390 struct radeon_surface *surf)
2395 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
2397 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) &&
2398 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) {
2400 surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
2401 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
2404 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode);
2467 struct radeon_surface *surf,
2471 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) {
2476 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) {
2479 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) {
2482 if (!surf->array_size) {
2486 surf->array_size = next_power_of_two(surf->array_size);
2488 switch (surf->nsamples) {
2500 if (surf->npix_y > 1) {
2505 if (surf->npix_z > 1) {
2510 if (surf->npix_z > 1) {
2515 surf->array_size = 8;
2517 surf->array_size = 6;
2523 if (surf->npix_y > 1) {
2536 struct radeon_surface *surf)
2541 type = RADEON_SURF_GET(surf->flags, TYPE);
2542 mode = RADEON_SURF_GET(surf->flags, MODE);
2544 r = radeon_surface_sanity(surf_man, surf, type, mode);
2548 return surf_man->surface_init(surf_man, surf);
2553 struct radeon_surface *surf)
2558 type = RADEON_SURF_GET(surf->flags, TYPE);
2559 mode = RADEON_SURF_GET(surf->flags, MODE);
2561 r = radeon_surface_sanity(surf_man, surf, type, mode);
2565 return surf_man->surface_best(surf_man, surf);