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Searched refs:nPRIV (Results 1 - 11 of 11) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm0plus.h302 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
313 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
314 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm4.h388 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
403 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
404 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_sc300.h319 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
330 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
331 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm3.h319 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
330 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
331 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm23.h325 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
336 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
337 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm35p.h450 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
469 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
470 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm33.h450 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
469 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
470 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm7.h403 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
418 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
419 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_starmc1.h461 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
480 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
481 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm85.h465 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
500 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
501 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
H A Dcore_cm55.h460 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ member
479 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
480 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */

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