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/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm85.h366 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
369 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
372 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
375 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
378 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
428 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
431 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
434 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
437 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
440 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm55.h366 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
369 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
372 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
375 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
378 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
426 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
429 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
432 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
435 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
438 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm4.h290 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
293 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
296 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
299 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
302 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
351 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
354 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
357 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
360 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
363 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm35p.h356 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
359 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
362 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
365 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
368 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
416 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
419 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
422 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
425 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
428 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm33.h356 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
359 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
362 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
365 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
368 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
416 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
419 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
422 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
425 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
428 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm3.h228 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
231 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
234 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
237 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
240 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
285 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
288 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
291 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
294 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
297 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_sc300.h228 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
231 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
234 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
237 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
240 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
285 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
288 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
291 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
294 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
297 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm23.h249 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
252 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
255 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
258 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
312 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
334 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Po
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H A Dcore_starmc1.h367 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
370 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
373 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
376 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
379 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
427 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
430 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
433 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
436 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
439 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm7.h305 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
308 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
311 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
314 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
317 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
366 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
369 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
372 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
375 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
378 #define xPSR_Q_Msk (1UL << xPSR_Q_Po
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H A Dcore_cm1.h215 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
218 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
221 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
224 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
266 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
269 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
272 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
275 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
278 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
300 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Po
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H A Dcore_cm0.h215 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
218 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
221 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
224 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
266 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
269 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
272 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
275 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
278 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
300 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Po
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H A Dcore_cm0plus.h226 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
229 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
232 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
235 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
289 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
311 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Po
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H A Dcore_sc000.h226 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
229 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
232 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
235 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
277 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
280 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
283 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
286 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
289 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
311 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Po
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/third_party/musl/porting/liteos_a_newlib/kernel/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/porting/uniproton/kernel/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/porting/liteos_m/kernel/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/porting/liteos_a/kernel/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/porting/liteos_m_iccarm/kernel/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/include/sys/
H A Dprctl.h106 #define PR_SET_PTRACER_ANY (-1UL)
144 #define PR_SPEC_PRCTL (1UL << 0)
145 #define PR_SPEC_ENABLE (1UL << 1)
146 #define PR_SPEC_DISABLE (1UL << 2)
147 #define PR_SPEC_FORCE_DISABLE (1UL << 3)
148 #define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
151 #define PR_PAC_APIAKEY (1UL << 0)
152 #define PR_PAC_APIBKEY (1UL << 1)
153 #define PR_PAC_APDAKEY (1UL << 2)
154 #define PR_PAC_APDBKEY (1UL <<
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/third_party/musl/src/signal/
H A Dblock.c7 -1UL, -1UL, -1UL, -1UL
9 -1UL, -1UL
11 -1UL
20 0x7fffffff, 0xfffffffc, -1UL, -1UL
26 0xfffffffc7fffffff, -1UL
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/third_party/mesa3d/include/android_stub/android/
H A Dhardware_buffer.h171 AHARDWAREBUFFER_USAGE_CPU_READ_NEVER = 0UL,
176 AHARDWAREBUFFER_USAGE_CPU_READ_RARELY = 2UL,
181 AHARDWAREBUFFER_USAGE_CPU_READ_OFTEN = 3UL,
189 AHARDWAREBUFFER_USAGE_CPU_WRITE_NEVER = 0UL << 4,
194 AHARDWAREBUFFER_USAGE_CPU_WRITE_RARELY = 2UL << 4,
199 AHARDWAREBUFFER_USAGE_CPU_WRITE_OFTEN = 3UL << 4,
204 AHARDWAREBUFFER_USAGE_GPU_SAMPLED_IMAGE = 1UL << 8,
206 AHARDWAREBUFFER_USAGE_GPU_FRAMEBUFFER = 1UL << 9,
239 AHARDWAREBUFFER_USAGE_PROTECTED_CONTENT = 1UL << 14,
241 AHARDWAREBUFFER_USAGE_VIDEO_ENCODE = 1UL << 1
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/third_party/mesa3d/src/imagination/vulkan/winsys/pvrsrvkm/
H A Dpvr_srv_bridge.h39 #define PVR_SRV_BRIDGE_SRVCORE 1UL
41 #define PVR_SRV_BRIDGE_SRVCORE_CONNECT 0UL
42 #define PVR_SRV_BRIDGE_SRVCORE_DISCONNECT 1UL
45 #define PVR_SRV_BRIDGE_SYNC 2UL
47 #define PVR_SRV_BRIDGE_SYNC_ALLOCSYNCPRIMITIVEBLOCK 0UL
48 #define PVR_SRV_BRIDGE_SYNC_FREESYNCPRIMITIVEBLOCK 1UL
50 #define PVR_SRV_BRIDGE_MM 6UL
52 #define PVR_SRV_BRIDGE_MM_PMRUNREFUNLOCKPMR 8UL
53 #define PVR_SRV_BRIDGE_MM_PHYSMEMNEWRAMBACKEDLOCKEDPMR 10UL
54 #define PVR_SRV_BRIDGE_MM_DEVMEMINTCTXCREATE 15UL
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/third_party/python/Modules/_decimal/libmpdec/
H A Dconstants.c79 const mpd_uint_t mpd_moduli[3] = {2113929217UL, 2013265921UL, 1811939329UL};
80 const mpd_uint_t mpd_roots[3] = {5UL, 31UL, 13UL};
85 {4293885170U, 2181570688U, 16352U}, /* ((long double) 1 / 2113929217UL) */
86 {1698898177U, 2290649223U, 16352U}, /* ((long double) 1 / 2013265921UL) */
87 {2716021846U, 2545165803U, 16352U} /* ((long double) 1 / 1811939329UL) */
93 const mpd_uint_t INV_P1_MOD_P2 = 2013265901UL;
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/third_party/curl/include/curl/
H A Dsystem.h67 # define CURL_SUFFIX_CURL_OFF_TU UL
76 # define CURL_SUFFIX_CURL_OFF_TU UL
85 # define CURL_SUFFIX_CURL_OFF_TU UL
100 # define CURL_SUFFIX_CURL_OFF_TU UL
109 # define CURL_SUFFIX_CURL_OFF_TU UL
131 # define CURL_SUFFIX_CURL_OFF_TU UL
140 # define CURL_SUFFIX_CURL_OFF_TU UL
157 # define CURL_SUFFIX_CURL_OFF_TU UL
196 # define CURL_SUFFIX_CURL_OFF_TU UL
228 # define CURL_SUFFIX_CURL_OFF_TU UL
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