Searched refs:TPR (Results 1 - 11 of 11) sorted by relevance

/third_party/typescript/tests/baselines/reference/
H A D	mappedTypeModifiers.js	5 type TPR = { readonly a?: number, readonly b?: string }; 11 var v00: keyof TPR; 30 var v04: TPR; 36 var v04: { [P in keyof TPR]: TPR[P] } 37 var v04: Pick<TPR, keyof T>;
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A D	HexagonISelLowering.cpp	348 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult() local 350 // TPR = (Chain, Glue) in LowerCallResult() 354 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult() 355 Glue = TPR.getValue(1); in LowerCallResult() 356 Chain = TPR.getValue(0); in LowerCallResult()
/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm4.h	837 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 847 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 848 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_sc300.h	755 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 765 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 766 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm3.h	772 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 782 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 783 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm35p.h	1045 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1068 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1069 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm33.h	1045 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1068 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1069 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm7.h	1056 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1066 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1067 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_starmc1.h	1106 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1125 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1126 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm85.h	1149 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1172 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1173 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
H A D	core_cm55.h	1149 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */ member 1172 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ 1173 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024