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Searched refs:RNR (Results 1 - 14 of 14) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A Darmv8m_mpu.h296 mpu->RNR = rnr; in ARM_MPU_ClrRegionEx()
326 mpu->RNR = rnr; in ARM_MPU_SetRegionEx()
377 mpu->RNR = rnr; in ARM_MPU_LoadEx()
383 mpu->RNR = rnrBase; in ARM_MPU_LoadEx()
391 mpu->RNR = rnrBase; in ARM_MPU_LoadEx()
H A Darmv7m_mpu.h218 MPU->RNR = rnr; in ARM_MPU_ClrRegion()
239 MPU->RNR = rnr; in ARM_MPU_SetRegionEx()
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_sc000.h545 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
573 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
574 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
H A Dcore_cm23.h859 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
895 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
896 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
967 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
986 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
987 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_cm0plus.h529 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
557 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
558 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
H A Dcore_cm35p.h1453 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1495 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1496 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1570 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
1593 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1594 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_cm33.h1453 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1495 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1496 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1570 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
1593 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1594 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_starmc1.h1550 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1592 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1593 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1664 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
1687 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1688 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_cm4.h1214 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1248 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1249 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
H A Dcore_sc300.h1132 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1166 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1167 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
H A Dcore_cm3.h1149 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1183 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1184 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
H A Dcore_cm85.h2929 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
2971 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
2972 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
3046 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
3069 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
3070 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_cm55.h2905 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
2947 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
2948 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
3022 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ member
3045 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
3046 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
H A Dcore_cm7.h1433 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ member
1467 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1468 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */

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