Searched refs:RBAR (Results 1 - 14 of 14) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/m-profile/
H A D	armv7m_mpu.h	182 uint32_t RBAR; //!< The region base address register value (RBAR) member 223 * \param rbar Value for RBAR register. 228 MPU->RBAR = rbar; in ARM_MPU_SetRegion() 234 * \param rbar Value for RBAR register. 240 MPU->RBAR = rbar; in ARM_MPU_SetRegionEx() 266 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); in ARM_MPU_Load() 270 ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cn in ARM_MPU_Load() [all...]
H A D	armv8m_mpu.h	183 uint32_t RBAR; /*!< Region Base Address Register value */ member 321 * \param rbar Value for RBAR register. 327 mpu->RBAR = rbar; in ARM_MPU_SetRegionEx() 333 * \param rbar Value for RBAR register. 344 * \param rbar Value for RBAR register. 378 ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); in ARM_MPU_LoadEx() 386 ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); in ARM_MPU_LoadEx() 394 ARM_MPU_OrderedMemcpy(&(mpu->RBAR) in ARM_MPU_LoadEx() [all...]
/third_party/cmsis/CMSIS/Core/Include/
H A D	core_sc000.h	546 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 577 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 578 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 580 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 581 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 583 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 584 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
H A D	core_cm23.h	860 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 899 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 900 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 902 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 903 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 905 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 906 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 908 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 909 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 968 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_cm0plus.h	530 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 561 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ 562 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 564 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 565 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 567 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 568 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
H A D	core_cm35p.h	1454 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1499 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 1500 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 1502 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 1503 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 1505 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 1506 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 1508 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 1509 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 1571 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_cm33.h	1454 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1499 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 1500 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 1502 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 1503 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 1505 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 1506 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 1508 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 1509 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 1571 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_starmc1.h	1551 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1596 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 1597 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 1599 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 1600 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 1602 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 1603 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 1605 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 1606 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 1665 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_cm4.h	1215 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1252 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1253 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1255 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1256 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1258 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1259 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
H A D	core_sc300.h	1133 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1170 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1171 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1173 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1174 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1176 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1177 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
H A D	core_cm3.h	1150 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1187 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1188 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1190 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1191 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1193 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1194 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
H A D	core_cm85.h	2930 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 2975 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 2976 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 2978 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 2979 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 2981 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 2982 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 2984 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 2985 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 3047 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_cm55.h	2906 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 2951 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ 2952 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ 2954 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ 2955 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ 2957 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ 2958 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ 2960 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ 2961 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ 3023 __IOM uint32_t RBAR; /*!< Offse member [all...]
H A D	core_cm7.h	1434 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ member 1471 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ 1472 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 1474 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ 1475 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 1477 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ 1478 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024