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Searched refs:MVFR2 (Results 1 - 9 of 9) sorted by relevance

/third_party/vixl/src/aarch32/
H A Dinstructions-aarch32.cc367 case MVFR2: in GetName()
368 return "MVFR2"; in GetName()
H A Dinstructions-aarch32.h904 MVFR2 = 0x5,
919 case MVFR2:
/third_party/cmsis/CMSIS/Core/Include/
H A Dcore_cm35p.h556 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
1659 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
1770 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1771 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_cm33.h556 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
1659 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
1770 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1771 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_cm7.h500 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
1533 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
1620 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1621 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_starmc1.h568 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
1753 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
1864 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1865 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_cm4.h1314 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
1401 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1402 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_cm85.h588 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
3135 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
3252 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
3253 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
H A Dcore_cm55.h567 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ member
3111 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ member
3228 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
3229 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */

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