Searched refs:MVFR1 (Results 1 - 9 of 9) sorted by relevance

/third_party/vixl/src/aarch32/
H A D	instructions-aarch32.cc	369 case MVFR1: in GetName() 370 return "MVFR1"; in GetName()
H A D	instructions-aarch32.h	905 MVFR1 = 0x6, 920 case MVFR1:
/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm35p.h	555 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 1658 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 1757 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 1758 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 1760 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1761 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1763 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1764 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1766 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1767 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1 [all...]
H A D	core_cm33.h	555 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 1658 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 1757 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 1758 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 1760 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1761 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1763 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1764 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1766 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1767 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1 [all...]
H A D	core_cm7.h	499 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 1532 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 1607 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 1608 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 1610 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1611 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1613 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1614 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1616 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1617 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1 [all...]
H A D	core_cm85.h	587 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 3134 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 3233 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 3234 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 3236 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 3237 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 3239 #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ 3240 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ 3242 #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ 3243 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1 [all...]
H A D	core_cm55.h	566 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 3110 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 3209 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 3210 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 3212 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 3213 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 3215 #define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ 3216 #define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ 3218 #define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ 3219 #define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1 [all...]
H A D	core_starmc1.h	567 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ member 1752 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 1851 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 1852 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 1854 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1855 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1857 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1858 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1860 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1861 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1 [all...]
H A D	core_cm4.h	1313 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ member 1388 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */ 1389 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */ 1391 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ 1392 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */ 1394 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ 1395 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */ 1397 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */ 1398 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024