Searched refs:ITCTRL (Results 1 - 10 of 10) sorted by relevance

/third_party/cmsis/CMSIS/Core/Include/
H A D	core_cm35p.h	1053 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ member 1117 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ 1118 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ 1290 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1409 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1410 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm33.h	1053 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ member 1117 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ 1118 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ 1290 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1409 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1410 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm4.h	1067 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1167 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1168 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_sc300.h	985 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1085 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1086 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm3.h	1002 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1102 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1103 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm23.h	696 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 815 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 816 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm85.h	1157 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ member 1221 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ 1222 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ 1962 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 2081 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 2082 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm55.h	1157 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control Register */ member 1221 #define ITM_ITCTRL_IME_Pos 0U /*!< ITM ITCTRL: IME Position */ 1222 #define ITM_ITCTRL_IME_Msk (1UL /*<< ITM_ITCTRL_IME_Pos*/) /*!< ITM ITCTRL: IME Mask */ 1938 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 2057 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 2058 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_cm7.h	1286 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1386 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1387 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
H A D	core_starmc1.h	1387 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ member 1506 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */ 1507 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */

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Indexes created Thu Nov 07 10:32:03 CST 2024